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SN8P1800
8-bit micro-controller build-in 12-bit ADC + 72 dots LCD driver
SN8P1800 Series
USER'S MANUAL
General Release Specification
SN8P1808
SONiX 8-Bit Micro-Controller
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.
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8-bit micro-controller build-in 12-bit ADC + 72 dots LCD driver
AMENDMENT HISTORY
Version VER 1.90 VER 1.93 Date Sep. 2002 Feb. 2003 Description V1.90 first issue 1. Extend chip operating temperature from "0C ~ +70C" to "-20C ~ +70C". 2. Change the description of ADD M,A instruction from "M 3. Add ADC grade. 4. Change bit name and initial value of RBANK register. 5. Change "ACC can't be access by "B0MOV" instruction" to "ACC can't be access by "B0MOV" instruction during the instant addressing mode". 6. Correct the description of STKnH. 7. Correct the bit definition of INTEN register. 8. Change "The low-speed clock frequency is supplied through on-chip RC oscillator circuit" to "The low-speed clock frequency is supplied through external low clock oscillator (32.768K) by crystal or RC mode". 9. Change all "internal low-speed clock" to "external low-speed clock". 10. 11. Correct the description of "TC0 CLOCK FREQUENCY OUTPUT" section. Correct the description of "TC1 CLOCK FREQUENCY OUTPUT" section. M+A" to "M A+M"
12. SCKMD = 1 means SIO is in SLAVE mode. SCKMD = 0 means SIO is in MASTER mode. 13. 14. 15. 16. 17. 18. 19. 20. VER 1.94 Sep. 2003 Remove "SIO clock and SPI clock are compatible". Remove this line: "B0MOV A, P2". P2 of SN8P1808 is output only. Note: The clock source of LCD driver is external low clock. Modify the description ADR register. Modify ADB's output data table. Correct an error of template code: "b0bclr FWDRST" Add a notice about OSCM register access cycle. Add slow mode (high clock stop and LVD OFF) operating current. "b0bset FWDRST".
1. Correct RAM Bank value. 2. Correct EOC description. 3. Correct watchdog timer overflow time. 4. Correct POP operand. 5. Correct ADCKS table. 6. Modify figure 11-1 (adjust circuit of LCD contrast) and related description. 7. Add new section about checksum calculate must avoid 04H~07H 8. Correct description of Port6 as I/O port in Chapter 10. 9. Add WTCKS bit in OSCM register 10. Add TC0CKS/TC1CKS in TC0M/TC1M 11. Reserved Last 16 word ROM addresses
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8-bit micro-controller build-in 12-bit ADC + 72 dots LCD driver
12. Add SIOM Table and Note for SIO Rate 13. Remove register bit description 14. Modify TC0M description 15. Modify TC1M description 16. Modify PWM description 17. Modify ADC Frequency description. 18. Change watchdog over flow table. 19. Change Code option table Chapter 2 20. Add ADC current consumption 21. Add LVD detect voltage 22. Modify electrical characteristic table 23. Remove approval sheet. 24. Remove PCB layout notice section. 25. Modify the description of INTRQ register. 26. Modify the calculation formula of SIOR and SIO clock.
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Table of Contents
AMENDMENT HISTORY .............................................................................................................. 2
1
PRODUCT OVERVIEW ................................................................................................... 10
GENERAL DESCRIPTION ......................................................................................................... 10 FEATURES SELECTION TABLE ............................................................................................... 10 ADC GRADE TABLE................................................................................................................... 10 FEATURES................................................................................................................................. 11 SYSTEM BLOCK DIAGRAM ...................................................................................................... 12 PIN ASSIGNMENT ..................................................................................................................... 13 PIN DESCRIPTIONS .................................................................................................................. 14 PIN CIRCUIT DIAGRAMS .......................................................................................................... 15
2 3
CODE OPTION TABLE ................................................................................................... 17
ADDRESS SPACES ........................................................................................................ 18
PROGRAM MEMORY (ROM)..................................................................................................... 18 OVERVIEW ............................................................................................................................. 18 USER RESET VECTOR ADDRESS (0000H).......................................................................... 19 INTERRUPT VECTOR ADDRESS (0008H) ............................................................................ 19 CHECKSUM CALCULATION .................................................................................................. 21 GENERAL PURPOSE PROGRAM MEMORY AREA.............................................................. 22 LOOKUP TABLE DESCRIPTION............................................................................................ 22 JUMP TABLE DESCRIPTION................................................................................................. 24 DATA MEMORY (RAM) .............................................................................................................. 26 OVERVIEW ............................................................................................................................. 26 RAM BANK SELECTION ........................................................................................................ 27 WORKING REGISTERS............................................................................................................. 28 H, L REGISTERS .................................................................................................................... 28 SONiX TECHNOLOGY CO., LTD
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Y, Z REGISTERS .................................................................................................................... 29 X REGISTERS ........................................................................................................................ 30 R REGISTERS ........................................................................................................................ 30 PROGRAM FLAG ....................................................................................................................... 31 CARRY FLAG ......................................................................................................................... 31 DECIMAL CARRY FLAG......................................................................................................... 31 ZERO FLAG ............................................................................................................................ 31 ACCUMULATOR ........................................................................................................................ 32 STACK OPERATIONS................................................................................................................ 33 OVERVIEW ............................................................................................................................. 33 STACK REGISTERS............................................................................................................... 34 STACK OPERATION EXAMPLE............................................................................................. 35 PROGRAM COUNTER............................................................................................................... 36 ONE ADDRESS SKIPPING .................................................................................................... 37 MULTI-ADDRESS JUMPING .................................................................................................. 38
4 5 6
ADDRESSING MODE...................................................................................................... 39
OVERVIEW................................................................................................................................. 39 IMMEDIATE ADDRESSING MODE ........................................................................................ 39 DIRECTLY ADDRESSING MODE .......................................................................................... 39 INDIRECTLY ADDRESSING MODE....................................................................................... 39 TO ACCESS DATA in RAM BANK 0....................................................................................... 40 TO ACCESS DATA in RAM BANK 1....................................................................................... 40 TO ACCESS DATA in RAM BANK 15 (LCD RAM) ................................................................. 40
SYSTEM REGISTER ....................................................................................................... 41
OVERVIEW................................................................................................................................. 41 SYSTEM REGISTER ARRANGEMENT (BANK 0) ..................................................................... 41 BYTES of SYSTEM REGISTER.............................................................................................. 41 BITS of SYSTEM REGISTER ................................................................................................. 42
POWER ON RESET ........................................................................................................ 44
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OVERVIEW................................................................................................................................. 44 EXTERNAL RESET DESCRIPTION........................................................................................... 45 LOW VOLTAGE DETECTOR (LVD) DESCRIPTION.................................................................. 46
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OSCILLATORS................................................................................................................ 47
OVERVIEW................................................................................................................................. 47 CLOCK BLOCK DIAGRAM ..................................................................................................... 47 OSCM REGISTER DESCRIPTION ......................................................................................... 48 OPTION REGISTER DESCRIPTION ...................................................................................... 48 EXTERNAL HIGH-SPEED OSCILLATOR............................................................................... 49 OSCILLATOR MODE CODE OPTION .................................................................................... 49 OSCILLATOR DEVIDE BY 2 CODE OPTION......................................................................... 49 OSCILLATOR SAFE GUARD CODE OPTION ....................................................................... 49 SYSTEM OSCILLATOR CIRCUITS ........................................................................................ 50 External RC Oscillator Frequency Measurement .................................................................... 51 SYSTEM MODE DESCRIPTION ................................................................................................ 52 OVERVIEW ............................................................................................................................. 52 NORMAL MODE ..................................................................................................................... 52 SLOW MODE .......................................................................................................................... 52 GREEN MODE........................................................................................................................ 52 POWER DOWN MODE........................................................................................................... 52 SYSTEM MODE CONTROL ....................................................................................................... 53 SN8P1800 SYSTEM MODE BLOCK DIAGRAM ..................................................................... 53 SYSTEM MODE SWITCHING ................................................................................................ 54 WAKEUP TIME........................................................................................................................... 55 OVERVIEW ............................................................................................................................. 55 HARDWARE WAKEUP ........................................................................................................... 55
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TIMERS COUNTERS....................................................................................................... 56
WATCHDOG TIMER (WDT) ....................................................................................................... 56 BASIC TIMER 0 ( T0 ) ................................................................................................................ 57 OVERVIEW ............................................................................................................................. 57 T0M REGISTER DESCRIPTION ............................................................................................ 57 T0C COUNTING REGISTER .................................................................................................. 58 SONiX TECHNOLOGY CO., LTD
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T0 BASIC TIMER OPERATION SEQUENCE ......................................................................... 59 TIMER COUNTER 0 (TC0) ......................................................................................................... 60 OVERVIEW ............................................................................................................................. 60 TC0M MODE REGISTER........................................................................................................ 61 TC0C COUNTING REGISTER................................................................................................ 62 TC0R AUTO-LOAD REGISTER .............................................................................................. 63 TC0 TIMER COUNTER OPERATION SEQUENCE................................................................ 64 TC0 CLOCK FREQUENCY OUTPUT (BUZZER).................................................................... 66 TC0OUT FREQUENCY TABLE .................................................................................................. 67 TIMER COUNTER 1 (TC1) ......................................................................................................... 69 OVERVIEW ............................................................................................................................. 69 TC1M MODE REGISTER........................................................................................................ 70 TC1C COUNTING REGISTER................................................................................................ 71 TC1R AUTO-LOAD REGISTER .............................................................................................. 72 TC1 TIMER COUNTER OPERATION SEQUENCE................................................................ 73 TC1 CLOCK FREQUENCY OUTPUT (BUZZER).................................................................... 75 PWM FUNCTION DESCRIPTION .............................................................................................. 76 OVERVIEW ............................................................................................................................. 76 PWM PROGRAM DESCRIPTION........................................................................................... 77
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INTERRUPT..................................................................................................................... 78
OVERVIEW................................................................................................................................. 78 INTEN INTERRUPT ENABLE REGISTER ................................................................................. 79 INTRQ INTERRUPT REQUEST REGISTER.............................................................................. 79 INTERRUPT OPERATION DESCRIPTION ................................................................................ 80 GIE GLOBAL INTERRUPT OPERATION ............................................................................... 80 INT0 (P0.0) INTERRUPT OPERATION .................................................................................. 81 INT1 (P0.1) INTERRUPT OPERATION .................................................................................. 81 INT2 (P0.2) INTERRUPT OPERATION .................................................................................. 82 T0 INTERRUPT OPERATION................................................................................................. 83 TC0 INTERRUPT OPERATION .............................................................................................. 84 TC1 INTERRUPT OPERATION .............................................................................................. 85 SIO INTERRUPT OPERATION............................................................................................... 86 MULTI-INTERRUPT OPERATION .......................................................................................... 87
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SERIAL INPUT/OUTPUT TRANSCEIVER (SIO) .................................................. 89
OVERVIEW................................................................................................................................. 89 SIOM MODE REGISTER............................................................................................................ 90 SIOB DATA BUFFER.................................................................................................................. 91 SIOR REGISTER DESCRIPTION .............................................................................................. 91 SIO MASTER OPERATING DESCRIPTION .............................................................................. 92 RISING EDGE TRANSMITTER/RECEIVER MODE................................................................ 92 FALLING EDGE TRANSMITTER/RECEIVER MODE ............................................................. 93 RISING EDGE RECEIVER MODE .......................................................................................... 94 FALLING EDGE RECEIVER MODE ....................................................................................... 95 SIO SLAVE OPERATING DESCRIPTION.................................................................................. 96 RISING EDGE TRANSMITTER/RECEIVER MODE................................................................ 97 FALLING EDGE TRANSMITTER/RECEIVER MODE ............................................................. 98 RISING EDGE RECEIVER MODE .......................................................................................... 99 FALLING EDGE RECEIVER MODE ..................................................................................... 100 SIO INTERRUPT OPERATION DESCRIPTION....................................................................... 101
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I/O PORT............................................................................................................. 102
OVERVIEW............................................................................................................................... 102 I/O PORT FUNCTION TABLE .................................................................................................. 103 PULL-UP RESISTOR (PNUR) REGISTER ............................................................................... 103 I/O PORT MODE ...................................................................................................................... 104 THE P0.3~P0.5 DISCRIPTION ................................................................................................. 105 THE PORT2 DISCRIPTION...................................................................................................... 106 THE PORT3 DISCRIPTION...................................................................................................... 107 OPTION Register .................................................................................................................. 107 THE PORT6 DISCRIPTION...................................................................................................... 108 LCDM Register...................................................................................................................... 108 I/O PORT DATA REGISTER .................................................................................................... 110
12
LCD DRIVER....................................................................................................... 112
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LCDM REGISTER .................................................................................................................... 112 LCD TIMING ............................................................................................................................. 113 LCD RAM LOCATION............................................................................................................... 114
13 14 15 16 17
8-CHANNEL ANALOG TO DIGITAL CONVERTER........................................... 115
OVERVIEW............................................................................................................................... 115 ADM REGISTER....................................................................................................................... 116 ADR REGISTERS..................................................................................................................... 116 ADB REGISTERS ..................................................................................................................... 116 ADC CONVERTING TIME ........................................................................................................ 118 ADC CIRCUIT........................................................................................................................... 119
CODING ISSUE .................................................................................................. 120
TEMPLATE CODE.................................................................................................................... 120 CHIP DECLARATION IN ASSEMBLER.................................................................................... 124 PROGRAM CHECK LIST ......................................................................................................... 124
INSTRUCTION SET TABLE ............................................................................... 125
ELECTRICAL CHARACTERISTIC ..................................................................... 126
ABSOLUTE MAXIMUM RATING .............................................................................................. 126 STANDARD ELECTRICAL CHARACTERISTIC ....................................................................... 126
PACKAGE INFORMATION ................................................................................ 127
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1
PRODUCT OVERVIEW
GENERAL DESCRIPTION
The SN8P1800 is an series of 8-bit micro-controller including SN8P1808. This series is utilized with CMOS technology fabrication and featured with low power consumption and high performance by its unique electronic structure. These chips are designed with the excellent IC structure including the large program memory OTP ROM, the massive data memory RAM, one 8-bit basic timer (T0), two 8-bit timer counters (TC0, TC1), high performance of real time clock timer (RTC) , a watchdog timer, up to seven interrupt sources (T0, TC0, TC1, SIO, INT0, INT1, INT2), an 8-channel ADC converter with 8-bit/12-bit resolution, two channel PWM output (PWM0, PWM1), tw0 channel buzzer output (BZ0, BZ1) and 8-level stack buffers. Besides, the user can choose desired oscillator configurations for the controller. There are four oscillator configurations to select for generating system clock, including High/Low speed crystal, ceramic resonator or cost-saving RC. SN8P1800 series is a dual clock system using a hi-speed crystal for normal mode operation and an external low speed crystal for slow mode, real time clock and LCD function.
FEATURES SELECTION TABLE
CHIP ROM RAM Stack 256 8 V Timer T0 TC0 TC1 SN8P1808 4K*16 V V 47 8ch I/O ADC DAC PWM Buzzer 2 1 SIO Wakeup Pin no. 10 LQPF64 Package
Table 1-1. Selection Table of SN8P1800
ADC GRADE TABLE
CHIP SN8P1808 PARAMETER Resolution No Mission Code Differential Nonlinearity (DNL) Resolution SN8P1808-12 No Mission Code Differential Nonlinearity (DNL)
Table 1-2. ADC Grade Table
MIN 8
MAX 12 12 16 12
UNITS Bits Bits LSB Bits Bits LSB
REMARK
10
12 4
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FEATURES
SN8P1808 Memory configuration OTP ROM size: 4K * 16 bits RAM size: 256 * 8 bits (bank 0 and bank 1) LCD RAM size: 24 * 3 bits I/O pin configuration Input only: P0, P3 Output only: P2 shared with LCD segment Bi-directional: P1, P4, P5, P6 Wakeup: P0, P1 Pull-up resisters: P0, P1, P3, P4, P5, P6 External interrupt: P0 Port 3 shared with LCD segment All LCD pins shared with the I/O pins 59 powerful instructions Four clocks per instruction cycle All of instructions are one word length. Most of instructions are one cycle only. Maximum instruction cycle is two. All ROM area JMP instruction. All ROM area lookup table function (MOVC) Support hardware multiplier (MUL). Seven interrupt sources Four internal interrupts: T0, TC0, TC1, SIO Three external interrupts: INT0, INT1, INT2 A real time clock timer An 8-bit basic timer with green mode wakeup function Two 8-bit timer counters with PWM or buzzer On chip watchdog timer Eight levels stack buffer An 8-channel ADC with 8-bit/12-bit resolution SIO function LCD driver: 1/3 duty, 1/2 bias. 3 common * 24 segment Dual clock system offers four operating modes External high clock: RC type up to 10 MHz External high clock: Crystal type up to 16 MHz External Low clock: Crystal 32768Hz Normal mode: Both high and low clock active. Slow mode: Low clock only. Sleep mode: Both high and low clock stop. Green mode: Periodical wakeup by timer. Package Chip form: LQFP 64 pins
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SYSTEM BLOCK DIAGRAM
PC IR FLAGS OTP ROM TIMING GENERATOR H-OSC L-OSC LCD DRIVER SEG. COM.
PWM1 ALU RAM PWM0 ACC SYSTEM REGISTER ADC
PWM1/Buzzer1 PWM0/Buzzer0 AIN0~AIN7
INTERRUPT CONTROL PORT 0
SIO TX/RX
TIMER & COUNTER PORT 6
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
Figure 1-1.Simplified System Block Diagram
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PIN ASSIGNMENT
SN8P1808 (LQFP64)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RST P0.0/INT0 P0.1/INT1 P0.2/INT2 P1.0 P1.1 P1.2 P1.3 VDD AVREFH P4.0/AIN0 P4.1/AIN1 P4.2/AIN2 P4.3/AIN3 P4.4/AIN4 P4.5/AIN5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 O 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG14/P3.6 SEG15/P3.7 SEG16/P2.0 SEG17/P2.1 SEG18/P2.2 SEG19/P2.3 SEG20/P2.4 SEG21/P2.5 SEG22/P2.6 SEG23/P2.7 COM0/P0.3 COM1/P0.4 COM2/P0.5 V1 V2 VLCD
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P4.6/AIN6 P4.7/AIN7 AVREFL AVSS VSS P5.0/SCK P5.1/SI P5.2/SO P5.3/BZ1/PWM1 P5.4/BZ0/PWM0 LXIN LXOUT XIN XOUT VDD VPP/VDD
VSS SEG0/P6.0 SEG1/P6.1 SEG2/P6.2 SEG3/P6.3 SEG4/P6.4 SEG5/P6.5 SEG6/P6.6 SEG7/P6.7 SEG8/P3.0 VDD SEG9/P3.1 SEG10/P3.2 SEG11/P3.3 SEG12/P3.4 SEG13/P3.5 SN8P1808Q
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PIN DESCRIPTIONS
PIN NAME VDD, VSS AVDD, AVSS VPP RST XIN, XOUT LXIN, LXOUT P0.0 / INT0 P0.1 / INT1 P0.2 / INT2 P0.3~ P0.5 P1.0 ~ P1.3 P2.0 ~ P2.7 P3.0 ~ P3.7 P4.0 ~ P4.7 P5.0 / SCK P5.1 / SI P5.2 / SO P5.3 / BZ1 / PWM1 P5.4 / BZ0 / PWM0 P6.0 ~ P6.7 AIN0 ~ AIN7 COM0 ~ COM2 SEG0 ~ SEG23 AvrefH,AverfL TYPE P P P I I, O I, O I I I I I/O O I I/O I/O I/O I/O I/O I/O I/O I O O I DESCRIPTION Power supply input pins for digital circuit. Power supply input pins for analog circuit. OTP ROM programming pin. Connect to VDD in normal operation. System reset input pin. Schmitt trigger structure, active "low", normal stay to "high". External oscillator pins. RC mode from XIN. Low speed (32768 Hz) oscillator pins. RC mode from LXIN. Port 0.0 and shared with INT0 trigger pin. (Schmitt trigger) / Built-in pull-up resisters. Port 0.1 and shared with INT1 trigger pin. (Schmitt trigger) / Built-in pull-up resisters. Port 0.2 and shared with INT2 trigger pin. (Schmitt trigger) / Built-in pull-up resisters. Port 0.3~Port 0.5 input pins and shared with LCD's COM0~COM2. (Schmitt trigger). Built-in pull-up resisters. Port 1.0~Port 1.3 bi-direction pins / Built-in pull-up resisters. Port 2.0~Port 2.7 output only port and shared with LCD's SEG16~SEG23. Port 3.0~Port 3.7 input port with pull-up resister and shared with LCD's SEG8~SEG15. Built-in pull-up resisters. Port 4.0~Port 4.7 bi-direction pins / Built-in pull-up resisters. Port 5.0 bi-direction pin and SIO's clock input/output / Built-in pull-up resisters. Port 5.1 bi-direction pin and SIO's data input / Built-in pull-up resisters. Port 5.2 bi-direction pin and SIO's data output / Built-in pull-up resisters. Port 5.3 bi-direction pin, TC1 / 2 signal output pin or PWM1 output pin. Built-in pull-up resisters. Port 5.4 bi-direction pin, TC0 / 2 signal output pin or PWM0 output pin. Built-in pull-up resisters. Port 6.0 ~ Port 6.7 bi-direction pins and shared with LCD's SEG0~SEG7. Enable pull-up resisters in input mode automatically. Analog signal input pins for ADC converter. LCD driver common pins. LCD driver segment pins. ADC's reference high / low voltage input pins. Table 1-3. SN8P1800 Pin Description
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PIN CIRCUIT DIAGRAMS
Port0.0~P0.2 structure
PUR
P0UR
Pin
Int. bus
Port0.3~P0.5 structure
PUR P0UR Int. bus
Pin LCD waveform
LCD Code Option
Port2 structure Latch Pin LCD waveform
LCD Code Option Int. bus
Port3 structure
PUR
Int. bus
Pin LCD waveform
P3LCD
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Port1,Port4,Port5 structure
PUR PnM PnM, PnUR
Pin
Latch
PnM PnM
Int. bus
Port6 structure
PUR PnM PnM
Pin
P6HSEG, P6LSEG PnM
Latch
Int. bus
PnM
LCD waveform
Figure 1-2. Pin Circuit Diagram
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Code Option High_Clk High_Clk / 2 OSG Watch_Dog LVD Security LCD
CODE OPTION TABLE
Content RC 32K X'tal 12M X'tal 4M X'tal Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Function Description Low cost RC for external high clock oscillator Low frequency, power saving crystal (e.g. 32.768K) for external high clock oscillator High speed crystal /resonator (e.g. 12M) for external high clock oscillator Standard crystal /resonator (e.g. 3.58M) for external high clock oscillator External high clock divided by two, Fosc = high clock / 2 Fosc = high clock Enable Oscillator Safe Guard function Disable Oscillator Safe Guard function Enable Watch Dog function Disable Watch Dog function Enable the low voltage detect Disable the low voltage detect Enable ROM code Security function Disable ROM code Security function Enable LCD function Disable LCD function Table 2-1. Code Option Table of SN8P1800
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ADDRESS SPACES
PROGRAM MEMORY (ROM)
OVERVIEW
ROM Maps for SN8P1800 devices provide 4K x 16 OTP memory that programmable by user. The SN8P1800 program memory is able to fetch instructions through 12-bit wide PC (Program Counter) and can look up ROM data by using ROM code registers (R, X, Y, Z). In standard configuration, the device's 4,096 x 16-bit program memory has four areas: 1-word reset vector addresses 1-word Interrupt vector addresses 5-words reserved area 4K words general purpose area All of the program memory is partitioned into two coding areas, located from 0000H to 0008H and from 0009H to 0FFEH. The former area is assigned for executing reset vector and interrupt vector. The later area is for storing instruction's OP-code and lookup table's data. User's program is in the last area (0010H~0FFEH). ROM Reset vector General purpose area
0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H . . 000FH 0010H 0011H . . 0FFEH 0FFFH
User reset vector Jump to user start address Jump to user start address Jump to user start address
Reserved Interrupt vector User interrupt vector User program
General purpose area
End of user program Reserved
Figure 3-1. ROM Address Structure
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USER RESET VECTOR ADDRESS (0000H)
A 1-word vector address area is used to execute system reset. After power on reset or watchdog timer overflow reset, then the chip will restart the program from address 0000h and all system registers will be set as default values. The following example shows the way to define the reset vector in the program memory. Example: After power on reset, external reset active or reset by watchdog timer overflow. CHIP SN8P1808 ORG JMP . ORG START: . . . . ENDP 0 START ; 0000H ; Jump to user program address. ; 0001H ~ 0007H are reserved
10H ; 0010H, The head of user program. ; User program
; End of program
INTERRUPT VECTOR ADDRESS (0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service is executed, the program counter (PC) value is stored in stack buffer and points to 0008h of program memory to execute the vectored interrupt. Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the program memory. Example 1: This demo program includes interrupt service routine and the user program is behind the interrupt service routine. CHIP SN8P1808 ORG JMP . ORG B0XCH PUSH . . . POP B0XCH RETI 0 START ; 0000H ; Jump to user program address. ; 0001H ~ 0007H are reserved ; Interrupt service routine ; B0XCH doesn't change C, Z flag ; Push 80H ~ 87H system registers
8 A, ACCBUF
; Pop 80H ~ 87H system registers A, ACCBUF ; End of interrupt service routine
START: . . . . JMP
; The head of user program. ; User program
START
; End of user program
ENDP
; End of program
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Example 2: The demo program includes interrupt service routine and the address of interrupt service routine is in a special address of general-purpose area. CHIP SN8P1808 ORG JMP . ORG JMP ORG START: . . . . JMP MY_IRQ: B0XCH PUSH . . . POP B0XCH RETI ENDP A, ACCBUF 0 START ; 0000H ; Jump to user program address. ; 0001H ~ 0007H are reserved
08 MY_IRQ 10H
; 0008H, Jump to interrupt service routine address
; 0010H, The head of user program. ; User program
START
; End of user program ;The head of interrupt service routine ; B0XCH doesn't change C, Z flag ; Push 80H ~ 87H system registers
; Pop 80H ~ 87H system registers A, ACCBUF ; End of interrupt service routine ; End of program
Remark: It is easy to get the rules of SONIX program from demo programs given above. These points are as following. 1. The address 0000H is a "JMP" instruction to make the program go to general-purpose ROM area. The 0004H~0007H are reserved. Users have to skip 0004H~0007H addresses. It is very important and necessary. 2. The interrupt service starts from 0008H. Users can put the whole interrupt service routine from 0008H (Example1) or to put a "JMP" instruction in 0008H then place the interrupt service routine in other general-purpose ROM area (Example2) to get more modularized coding style.
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CHECKSUM CALCULATION
The ROM addresses 0004H~0007H and last address are reserved area. User should avoid these addresses (0004H~0007H and last address) when calculate the Checksum value. Example: The demo program shows how to avoid 0004H~0007H when calculated Checksum from 00H to the end of user's code MOV A,#END_USER_CODE$L B0MOV END_ADDR1,A ;save low end address to end_addr1 MOV A,#END_USER_CODE$ M B0MOV END_ADDR2,A ;save middle end address to end_addr2 CLR Y ;set Y to ooH CLR Z ;set Z to 00H @@: CALL MOVC B0BSET ADD MOV ADC JMP AAA: INCMS JMP JMP END_CHECK: MOV CMPRS JMP MOV CMPRS JMP JMP YZ_CHECK: MOV CMPRS RET MOV CMPRS RET INCMS INCMS INCMS INCMS RET Y_ADD_1: INCMS NOP JMP CHECKSUM_END: .......... .......... END_USER_CODE: ;Label of program end Y @B ;increase Y ;jump to checksum calculate A,#04H A,Z A,#00H A,Y Z Z Z Z A,END_ADDR1 A,Z AAA A,END_ADDR2 A,Y AAA CHECKSUM_END ;check if Z = low end address ;if Not jump to checksum calculate ;if Yes, check if Y = middle end address ;if Not jump to checksum calculate ;if Yes checksum calculated is done. ;check if YZ=0004H ;check if Z=04H ;if Not return to checksum calculate ;if Yes, check if Y=00H ;if Not return to checksum calculate ;if Yes, increase 4 to Z Z @B Y_ADD_1 ;Z=Z+1 ;if Z!= 00H calculate to next address ;if Z=00H increase Y YZ_CHECK FC DATA1,A A,R DATA2,A END_CHECK ;call function of check yz value ; ;clear C glag ;add A to Data1 ;add R to Data2 ;check if the YZ address =
the end of code
;set YZ=0008H then return
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GENERAL PURPOSE PROGRAM MEMORY AREA
The 4089-word at ROM locations 0010H~0FFEH are used as general-purpose memory. The area is stored instruction's op-code and look-up table data. The SN8P1800 includes jump table function by using program counter (PC) and look-up table function by using ROM code registers (R, X, Y, Z). The boundary of program memory is separated by the high-byte program counter (PCH) every 100H. In jump table function and look-up table function, the program counter can't leap over the boundary by program counter automatically. Users need to modify the PCH value to "PCH+1" as the PCL overflow (from 0FFH to 000H).
LOOKUP TABLE DESCRIPTION
In the ROM's data lookup function, the X register is pointed to the highest 8-bit, Y register to the middle 8-bit and Z register to the lowest 8-bit data of ROM address. After MOVC instruction is executed, the low-byte data of ROM then will be stored in ACC and high-byte data stored in R register. Example: To look up the ROM data located "TABLE1".
B0MOV B0MOV MOVC
Y, #TABLE1$M Z, #TABLE1$L
INCMS JMP INCMS NOP @@: TABLE1: MOVC . DW DW DW
Z @F Y
. 0035H 5105H 2012H
; To set lookup table1's middle address ; To set lookup table1's low address. ; To lookup data, R = 00H, ACC = 35H ; ; Increment the index address for next address ; Z+1 ; Not overflow ; Z overflow (FFH 00), Y=Y+1 ; Not overflow ; ; To lookup data, R = 51H, ACC = 05H. ; ; To define a word (16 bits) data. ;" ;"
CAUSION: The Y register can't increase automatically if Z register cross boundary from 0xFF to 0x00. Therefore, user must take care such situation to avoid loop-up table errors. If Z register overflow, Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically. Note: Because the program counter (PC) is only 12-bit, the X register is useless in the application. Users can omit "B0MOV X, #TABLE1$H". SONiX ICE support more larger program memory addressing capability. So make sure X register is "0" to avoid unpredicted error in loop-up table operation. Example: INC_YZ Macro INC_YZ MACRO INCMS JMP INCMS NOP @@: ENDM
Z @F Y
; Z+1 ; Not overflow ; Y+1 ; Not overflow
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The other coding style of loop-up table is to add Y or Z index register by accumulator. Be careful if carry happen. Refer following example for detailed information: Example: Increase Y and Z register by B0ADD/ADD instruction B0MOV B0MOV B0MOV B0ADD B0BTS1 JMP INCMS NOP GETDATA: MOVC Y, #TABLE1$M Z, #TABLE1$L A, BUF Z, A FC GETDATA Y ; To set lookup table's middle address. ; To set lookup table's low address. ; Z = Z + BUF.
; Check the carry flag. ; FC = 0 ; FC = 1. Y+1.
TABLE1:
. DW DW DW
. 0035H 5105H 2012H
; ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 . . ; ; To define a word (16 bits) data. ;" ;"
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JUMP TABLE DESCRIPTION
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC value to get one new PCL. The new program counter (PC) points to a series jump instructions as a listing table. The way is easy to make a multi-stage program. When carry flag occurs after executing of "ADD PCL, A", it will not affect PCH register. Users have to check if the jump table leaps over the ROM page boundary or the listing file generated by SONIX assembly software. If the jump table leaps over the ROM page boundary (e.g. from xxFFH to xx00H), move the jump table to the top of next program memory page (xx00H). Here one page mean 256 words. Example : If PC = 0323H ORG B0ADD JMP JMP JMP JMP (PCH = 03HPCL = 23H) 0X0100 PCL, A A0POINT A1POINT A2POINT A3POINT ; The jump table is from the head of the ROM boundary ; PCL = PCL + ACC, the PCH can't be changed. ; ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT
In following example, the jump table starts at 0x00FD. When execute B0ADD PCL, A. If ACC = 0 or 1, the jump table points to the right address. If the ACC is larger then 1 will cause error because PCH doesn't increase one automatically. We can see the PCL = 0 when ACC = 2 but the PCH still keep in 0. The program counter (PC) will point to a wrong address 0x0000 and crash system operation. It is important to check whether the jump table crosses over the boundary (xxFFH to xx00H). A good coding style is to put the jump table at the start of ROM boundary (e.g. 0100H).
Example: If "jump table" crosses over ROM boundary will cause errors. ROM Address . . . 0X00FD 0X00FE 0X00FF 0X0100 0X0101 . .
. . . B0ADD JMP JMP JMP JMP . .
PCL, A A0POINT A1POINT A2POINT A3POINT
; PCL = PCL + ACC, the PCH can't be changed. ; ACC = 0 ; ACC = 1 ; ACC = 2 jump table cross boundary here ; ACC = 3
SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro is maybe wasting some ROM size. Notice the maximum jmp table number for this macro is limited under 254.
@JMP_A
MACRO IF JMP ORG ENDIF ADD ENDM
VAL (($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00) ($ | 0XFF) ($ | 0XFF) PCL, A
Note: "VAL" is the number of the jump table listing number.
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Example: "@JMP_A" application in SONIX macro file called "MACRO3.H". B0MOV @JMP_A JMP JMP JMP JMP JMP A, BUF0 5 A0POINT A1POINT A2POINT A3POINT A4POINT ; "BUF0" is from 0 to 4. ; The number of the jump table listing is five. ; If ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT ; ACC = 4, jump to A4POINT
If the jump table position is from 00FDH to 0101H, the "@JMP_A" macro will make the jump table to start from 0100h.
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DATA MEMORY (RAM)
OVERVIEW
The SN8P1808 has internally built-in the huge data memory up to 256 bytes for storing general purpose data and featured with LCD memory space up to 24 locations (24 * 3 bits) for displaying pattern.
256 * 8-bit general purpose area 128 * 8-bit system register area 24 * 3-bit LCD memory space
These memory are separated into bank 0, bank1 and bank 15. The user can program RBANK register of RAM bank selection bit to access all data in any of the three RAM banks. The bank 0 and bank1, using the first 128-byte location assigned as general-purpose area, and the remaining 128-byte in bank 0 as system register. The bank 15 is LCD RAM area designed for storing LCD display data.
000h BANK 0 07Fh 080h 0FFh 100h BANK 1 17Fh 200h 280h 300h 380h F00h BANK 15 F17h
RAM location General purpose area . . System register . End of bank 0 area General purpose area . End of bank 1 area " " " " " " " " LCD RAM area . End of LCD Ram
; 000h~07Fh of Bank 0 = To store general ; purpose data (128 bytes). ; 080h~0FFh of Bank 0 = To store system ; registers (128 bytes). ; Bank 1 = To store general purpose data. ; Bank 1 only has 128 bytes RAMs. ; reserved ;" ;" ;" ;" ;" ;" ;" ; Bank 15 = To store LCD display data ; (24 bytes). ;
Figure 3-2 RAM Location of SN8P1808 Note:1. The undefined locations of system register area are logic "high" after executing read instruction "MOV A, M". Note:2. The lower 24 locations of bank15 are used to store LCD display data and the other locations are reserved. The RAMs of LCD data area only have lowest 3-bit to be used. The highest 5-bit are undefined.
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RAM BANK SELECTION
The RBANK is a 1-bit register located at 87H in RAM bank 0. The user can access RAM data by using this register pointing to working RAM bank for ACC to read/write RAM data.
RBANK initial value = xxxx 0000 087H RBANK Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 RBNKS3 R/W Bit 2 RBNKS2 R/W Bit 1 RBNKS1 R/W Bit 0 RBNKS0 R/W
RBNKn: RAM bank selecting control bit. 0 = bank 0, 1 = bank 1.
Example: RAM bank selecting. ; BANK 0 CLR . ; BANK 1 MOV B0MOV . A, #1 RBANK, A RBANK
Note: "B0MOV" instruction can access the RAM of bank 0 in other bank situation directly. Example: Access RAM bank 0 in RAM bank 1. ; BANK 1 B0BSET B0MOV MOV . . MOV B0MOV RBNKS0 A, BUF0 BUF1, A . A, BUF1 BUF0, A ; Get into RAM bank 1 ; Read BUF0 data. BUF0 is in RAM bank0. ; Write BUF0 data to BUF1. BUF1 is in RAM bank1.
; Read BUF1 data and store in ACC. ; Write ACC data to BUF0.
Under bank 1 situation, using "B0MOV" instruction is an easy way to access RAM bank 0 data. User can make a habit to read/write system register (0087H~00FFH). Then user can access system registers without switching RAM bank. Example: To Access the system registers in bank 1 situation. ; BANK 1 B0BSET . MOV B0MOV . B0MOV MOV RBNKS0 . A, #0FFH P1, A A, P0 BUF1, A ; Get into RAM bank 1 ; Set all pins of P1 to be logic high.
; Read P0 data and store into BUF1 of RAM bank 1.
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WORKING REGISTERS
The locations 80H to 86H of RAM bank 0 in data memory stores the specially defined registers such as register H, L, R, X, Y, Z and PFLAG, respectively shown in the following table. These registers can use as the general purpose of working buffer and can also be used to access ROM's and RAM's data. For instance, all of the ROM's table can be looked-up with R, X, Y and Z registers. And the data of RAM memory can be indirectly accessed with H, L, Y and Z registers.
RAM
80H L R/W
81H H R/W
82H R R/W
83H Z R/W
84H Y R/W
85H X R/W
86H PFLAG R/W
H, L REGISTERS
The H and L are 8-bit register with two major functions. One is to use the registers as working register. The other is to use the registers as data pointer to access RAM's data. The @HL that is data point_0 index buffer located at address E6H in RAM bank_0. It employs H and L registers to addressing RAM location in order to read/write data through ACC. The Lower 4-bit of H register is pointed to RAM bank number and L register is pointed to RAM address number, respectively. The higher 4-bit data of H register is truncated in RAM indirectly access mode.
H initial value = 0000 0000 081H H Bit 7 HBIT7 R/W Bit 6 HBIT6 R/W Bit 5 HBIT5 R/W Bit 4 HBIT4 R/W Bit 3 HBIT3 R/W Bit 2 HBIT2 R/W Bit 1 HBIT1 R/W Bit 0 HBIT0 R/W
L initial value = 0000 0000 080H L Bit 7 LBIT7 R/W Bit 6 LBIT6 R/W Bit 5 LBIT5 R/W Bit 4 LBIT4 R/W Bit 3 LBIT3 R/W Bit 2 LBIT2 R/W Bit 1 LBIT1 R/W Bit 0 LBIT0 R/W
Example: If want to read a data from RAM address 20H of bank_0, it can use indirectly addressing mode to access data as following. B0MOV B0MOV B0MOV H, #00H L, #20H A, @HL ; To set RAM bank 0 for H register ; To set location 20H for L register ; To read a data into ACC
Example: Clear general-purpose data memory area of bank 0 using @HL register. CLR MOV B0MOV CLR_HL_BUF: CLR DECMS JMP CLR END_CLR: . . . . Page 28 @HL L CLR_HL_BUF @HL ; End of clear general purpose data memory area of bank 0 ; Clear @HL to be zero ; L - 1, if L = 0, finish the routine ; Not zero H A, #07FH L, A ; H = 0, bank 0 ; L = 7FH, the last address of the data memory area
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Y, Z REGISTERS
The Y and Z registers are the 8-bit buffers. There are three major functions of these registers. First, Y and Z registers can be used as working registers. Second, these two registers can be used as data pointers for @YZ register. Third, the registers can be address ROM location in order to look-up ROM data.
Y initial value = 0000 0000 084H Y Bit 7 YBIT7 R/W Bit 6 YBIT6 R/W Bit 5 YBIT5 R/W Bit 4 YBIT4 R/W Bit 3 YBIT3 R/W Bit 2 YBIT2 R/W Bit 1 YBIT1 R/W Bit 0 YBIT0 R/W
Z initial value = 0000 0000 083H Z Bit 7 ZBIT7 R/W Bit 6 ZBIT6 R/W Bit 5 ZBIT5 R/W Bit 4 ZBIT4 R/W Bit 3 ZBIT3 R/W Bit 2 ZBIT2 R/W Bit 1 ZBIT1 R/W Bit 0 ZBIT0 R/W
The @YZ that is data point_1 index buffer located at address E7H in RAM bank 0. It employs Y and Z registers to addressing RAM location in order to read/write data through ACC. The Lower 4-bit of Y register is pointed to RAM bank number and Z register is pointed to RAM address number, respectively. The higher 4-bit data of Y register is truncated in RAM indirectly access mode. Example: If want to read a data from RAM address 25H of bank 1, it can use indirectly addressing mode to access data as following. B0MOV B0MOV B0MOV Y, #01H Z, #25H A, @YZ ; To set RAM bank 1 for Y register ; To set location 25H for Z register ; To read a data into ACC
Example: Clear general-purpose data memory area of bank 1 using @YZ register. MOV B0MOV MOV B0MOV CLR_YZ_BUF: CLR DECMS JMP CLR END_CLR: . Note: Please consult the "LOOK-UP TABLE DESCRIPTION" about Y, Z register look-up table application. @YZ Z CLR_YZ_BUF @YZ ; End of clear general purpose data memory area of bank 0 ; Clear @YZ to be zero ; Y - 1, if Y= 0, finish the routine ; Not zero A, #1 Y, A A, #07FH Z, A
; Y = 1, bank 1 ; Y = 7FH, the last address of the data memory area
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X REGISTERS
The X register is the 8-bit buffer. There are two major functions of the register. First, X register can be used as working registers. Second, the X registers can be address ROM location in order to look-up ROM data. The SN8P1800's program counter only has 12-bit. In look-up table function, users can omit X register.
X initial value = 0000 0000 085H X Bit 7 XBIT7 R/W Bit 6 XBIT6 R/W Bit 5 XBIT5 R/W Bit 4 XBIT4 R/W Bit 3 XBIT3 R/W Bit 2 XBIT2 R/W Bit 1 XBIT1 R/W Bit 0 XBIT0 R/W
Note: Please consult the "LOOK-UP TABLE DESCRIPTION" about X register look-up table application.
R REGISTERS
The R register is the 8-bit buffer. There are two major functions of the register. First, R register can be used as working registers. Second, the R registers can be store high-byte data of look-up ROM data. After MOVC instruction executed, the high-byte data of a ROM address will be stored in R register and the low-byte data stored in ACC.
R initial value = 0000 0000 082H R Bit 7 RBIT7 R/W Bit 6 RBIT6 R/W Bit 5 RBIT5 R/W Bit 4 RBIT4 R/W Bit 3 RBIT3 R/W Bit 2 RBIT2 R/W Bit 1 RBIT1 R/W Bit 0 RBIT0 R/W
Note: Please consult the "LOOK-UP TABLE DESCRIPTION" about R register look-up table application.
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PROGRAM FLAG
The PFLAG includes carry flag (C), decimal carry flag (DC) and zero flag (Z). If the result of operating is zero or there is carry, borrow occurrence, then these flags will be set to PFLAG register.
PFLAG initial value = xxxx x000 086H PFLAG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 C R/W Bit 1 DC R/W Bit 0 Z R/W
CARRY FLAG
C = 1: If executed arithmetic addition with occurring carry signal or executed arithmetic subtraction without borrowing signal or executed rotation instruction with shifting out logic "1". C = 0: If executed arithmetic addition without occurring carry signal or executed arithmetic subtraction with borrowing signal or executed rotation instruction with shifting out logic "0".
DECIMAL CARRY FLAG
DC = 1: If executed arithmetic addition with occurring carry signal from low nibble or executed arithmetic subtraction without borrow signal from high nibble. DC = 0: If executed arithmetic addition without occurring carry signal from low nibble or executed arithmetic subtraction with borrow signal from high nibble.
ZERO FLAG
Z = 1: After operation, the content of ACC is zero. Z = 0: After operation, the content of ACC is not zero.
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ACCUMULATOR
The ACC is an 8-bits data register responsible for transferring or manipulating data between ALU and data memory. If the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register. ACC is not in data memory (RAM), so ACC can't be access by "B0MOV" instruction during the instant addressing mode.
Example: Read and write ACC value. ; Read ACC data and store in BUF data memory MOV . BUF, A .
; Write a immediate data into ACC MOV . A, #0FH .
; Write ACC data from BUF data memory MOV . A, BUF .
The PUSH and POP instructions don't store ACC value as any interrupt service executed. ACC must be exchanged to another data memory defined by users. Thus, once interrupt occurs, these data must be stored in the data memory based on the user's program as follows.
Example: ACC and working registers protection. ACCBUF INT_SERVICE: B0XCH PUSH. . . . POP B0XCH RETI A, ACCBUF . . ; Store ACC value ; Push instruction EQU 00H ; ACCBUF is ACC data buffer in bank 0.
; Pop instruction A, ACCBUF ; Re-load ACC ; Exit interrupt service vector
Notice: To save and re-load ACC data must be used "B0XCH" instruction, or the PLAGE value maybe modified by ACC.
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STACK OPERATIONS
OVERVIEW
The stack buffer of SN8P1800 has 8-level high area and each level is 12-bits length. This buffer is designed to save and restore program counter's (PC) data when interrupt service is executed. The STKP register is a pointer designed to point active level in order to save or restore data from stack buffer for kernel circuit. The STKnH and STKnL are the 12-bit stack buffers to store program counter (PC) data.
STACK BUFFER
PCH PCL
RET / RETI
CALL / interrupt STKP = 7 STKP = 6 STKP = 5 STKP = 4 STKP STK3H STK4H STK5H STK6H STK7H STK0H STK1H STK2H STKP STK3L STK4L STK5L STK6L STK7L STK0L STK1L STK2L
STKP + 1
STKP - 1 STKP = 3 STKP = 2 STKP = 1 STKP = 0
Figure 3-3 Stack-Save and Stack-Restore Operation
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STACK REGISTERS
The stack pointer (STKP) is a 4-bit register to store the address used to access the stack buffer, 12-bits data memory (STKnH and STKnL) set aside for temporary storage of stack addresses. The two stack operations are writing to the top of the stack (Stack-Save) and reading (Stack-Restore) from the top of stack. Stack-Save operation decrements the STKP and the Stack-Resotre operation increments one time. That makes the STKP always points to the top address of stack buffer and writes the last program counter value (PC) into the stack buffer. The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer (STKnH and STKnL) are located in the system register area bank 0.
STKP (stack pointer) initial value = 0xxx 1111 0DFH STKP Bit 7 GIE R/W Bit 6 Bit 5 Bit 4 Bit 3 STKPB3 R/W Bit 2 STKPB2 R/W Bit 1 STKPB1 R/W Bit 0 STKPB0 R/W
STKPBn: Stack pointer. (n = 0 ~ 3) GIE: Global interrupt control bit. 0 = disable, 1 = enable. More detail information is in interrupt chapter.
Example: Stack pointer (STKP) reset routine. MOV B0MOV A, #00001111B STKP, A
STKn (stack buffer) initial value = xxxx xxxx xxxx xxxx, 0F0H~0FFH STKnH Bit 7 Bit 6 Bit 5 -
STKn = STKnH + STKnL (n = 7 ~ 0) Bit 3 SnPC11 R/W Bit 2 SnPC10 R/W Bit 1 SnPC9 R/W Bit 0 SnPC8 R/W
Bit 4 -
0F0H~0FFH STKnL
Bit 7 SnPC7 R/W
Bit 6 SnPC6 R/W
Bit 5 SnPC5 R/W
Bit 4 SnPC4 R/W
Bit 3 SnPC3 R/W
Bit 2 SnPC2 R/W
Bit 1 SnPC1 R/W
Bit 0 SnPC0 R/W
STKnH: Store PCH data as interrupt or call executing. The n expressed 0 ~7. STKnL: Store PCL data as interrupt or call executing. The n expressed 0 ~7.
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STACK OPERATION EXAMPLE
The two kinds of Stack-Save operations to reference the stack pointer (STKP) and write the program counter contents (PC) into the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP is decremented and points to the next available stack location. The stack buffer stores the program counter about the op-code address. The Stack-Save operation is as following table. Stack Level 0 1 2 3 4 5 6 7 >8 STKP Register STKPB2 STKPB1
1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 -
STKPB3
1 1 1 1 1 1 1 1 -
STKPB0
1 0 1 0 1 0 1 0 -
Stack Buffer High Byte Low Byte
STK0H STK1H STK2H STK3H STK4H STK5H STK6H STK7H STK0L STK1L STK2L STK3L STK4L STK5L STK6L STK7L -
Description Stack Overflow
Table 3-1. STKP, STKnH and STKnL relative of Stack-Save Operation There is a Stack-Restore operation corresponding each push operation to restore the program counter (PC). The RETI instruction is for interrupt service routine. The RET instruction is for CALL instruction. When a Stack-Restore operation occurs, the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter (PC) to the program counter registers. The Stack-Restore operation is as following table. Stack Level 7 6 5 4 3 2 1 0 STKP Register STKPB2 STKPB1
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1
STKPB3
1 1 1 1 1 1 1 1
STKPB0
0 1 0 1 0 1 0 1
Stack Buffer High Byte Low Byte
STK7H STK6H STK5H STK4H STK3H STK2H STK1H STK0H STK7L STK6L STK5L STK4L STK3L STK2L STK1L STK0L
Description -
Table 3-2. STKP, STKnH and STKnL relative of Stack-Restore Operation
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PROGRAM COUNTER
The program counter (PC) is a 12-bit binary counter separated into the high-byte 4 bits and the low-byte 8 bits. This counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program counter is automatically incremented with each instruction during program execution. Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction is executed, the destination address will be inserted to bit 0 ~ bit 11.
PC Initial value = xxxx 0000 0000 0000 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 0 0 0 PCH Bit 8 0 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 Bit 3 0 0 PCL Bit 2 0 Bit 1 0 Bit 0 0
PC
PCH Initial value = xxxx 0000 0CFH PCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PC11 R/W Bit 2 PC10 R/W Bit 1 PC9 R/W Bit 0 PC8 R/W
PCL Initial value = 0000 0000 0CEH PCL Bit 7 PC7 R/W Bit 6 PC6 R/W Bit 5 PC5 R/W Bit 4 PC4 R/W Bit 3 PC3 R/W Bit 2 PC2 R/W Bit 1 PC1 R/W Bit 0 PC0 R/W
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ONE ADDRESS SKIPPING
There are 9 instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one address skipping function. If the result of these instructions is matched, the PC will add 2 steps to skip next instruction.
If the condition of bit test instruction is matched, the PC will add 2 steps to skip next instruction. B0BTS1 JMP . NOP B0MOV B0BTS0 JMP . NOP FC C0STEP ; Skip next instruction, if Carry_flag = 1 ; Else jump to C0STEP.
C0STEP:
A, BUF0 FZ C1STEP
; Move BUF0 value to ACC. ; Skip next instruction, if Zero flag = 0. ; Else jump to C1STEP.
C1STEP:
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. CMPRS JMP . NOP A, #12H C0STEP ; Skip next instruction, if ACC = 12H. ; Else jump to C0STEP.
C0STEP:
If the result after increasing or decreasing by 1 is 0xFF or 0x00, the PC will add 2 steps to skip next instruction. INCS instruction: INCS JMP ... NOP BUF0 C0STEP ; Jump to C0STEP if ACC is not zero.
C0STEP:
INCMS instruction: INCMS JMP ... NOP BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero.
C0STEP:
DECS instruction: DECS JMP ... NOP BUF0 C0STEP ; Jump to C0STEP if ACC is not zero.
C0STEP:
DECMS instruction: DECMS JMP ... NOP BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero.
C0STEP:
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MULTI-ADDRESS JUMPING
Users can jump round multi-address by either JMP instruction or ADD M, A instruction (M = PCL) to activate multi-address jumping function. If carry signal occurs after execution of ADD PCL, A, the carry signal will not affect PCH register.
Example: If PC = 0323H ; PC = 0323H MOV B0MOV . . . MOV B0MOV
(PCH = 03HPCL = 23H)
; PC = 0328H
A, #28H PCL, A . . . A, #00H PCL, A
; Jump to address 0328H
; Jump to address 0300H
Example: If PC = 0323H ; PC = 0323H B0ADD JMP JMP JMP JMP .
(PCH = 03HPCL = 23H)
PCL, A A0POINT A1POINT A2POINT A3POINT .
; PCL = PCL + ACC, the PCH cannot be changed. ; If ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT ;
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4
ADDRESSING MODE
OVERVIEW
The SN8P1800 provides three addressing modes to access RAM data, including immediate addressing mode, directly addressing mode and indirectly address mode. The main purpose of the three different modes is described in the following:
IMMEDIATE ADDRESSING MODE
The immediate addressing mode uses an immediate data to set up the location (MOV A, #I, B0MOV M,#I) in ACC or specific RAM. Immediate addressing mode MOV A, #12H ; To set an immediate data 12H into ACC
DIRECTLY ADDRESSING MODE
The directly addressing mode uses address number to access memory location (MOV A,12H, MOV 12H,A). Directly addressing mode B0MOV A, 12H ; To get a content of location 12H of bank 0 and save in ACC
INDIRECTLY ADDRESSING MODE
The indirectly addressing mode is to set up an address in data pointer registers (Y/Z) and uses MOV instruction to read/write data between ACC and @YZ register (MOV A,@YZ, MOV @YZ,A).
Example: Indirectly addressing mode with @YZ register CLR B0MOV B0MOV Y Z, #12H A, @YZ ; To clear Y register to access RAM bank 0. ; To set an immediate data 12H into Z register. ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC.
MOV B0MOV B0MOV B0MOV
A, #01H Y, A Z, #12H A, @YZ
; To set Y = 1 for accessing RAM bank 1. ; To set an immediate data 12H into Z register. ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC.
MOV B0MOV B0MOV B0MOV
A, #0FH Y, A Z, #12H A, @YZ
; To set Y = 15 for accessing RAM bank 15. ; To set an immediate data 12H into Z register. ; Use data pointer @YZ reads a data from RAM location 012H ; Into ACC.
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TO ACCESS DATA in RAM BANK 0
In the RAM bank 0, this area memory can be read/written by these three access methods.
Example 1: To use RAM bank0 dedicate instruction (Such as B0xxx instruction). B0MOV A, 12H ; To move content from location 12H of RAM bank 0 to ACC
Example 2: To use directly addressing mode (Through RBANK register). B0MOV MOV RBANK, #00H A, 12H ; To set RAM bank = 0 ; To move content from location 12H of RAM bank 0 to ACC
Example 3: To use indirectly addressing mode with @YZ register. CLR B0MOV B0MOV Y Z, #12H A, @YZ ; To clear Y register for accessing RAM bank 0. ; To set an immediate data 12H into Z register. ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC.
TO ACCESS DATA in RAM BANK 1
In the RAM bank 1, this area memory can be read/written by these two access methods.
Example 1: To use directly addressing mode (Through RBANK register). B0MOV MOV RBANK, #01H A, 12H ; To set RAM bank = 1 ; To move content from location 12H of RAM bank 1 to ACC
Example 2: To use indirectly addressing mode with @YZ register. MOV B0MOV B0MOV B0MOV A, #01H Y, A Z, #12H A, @YZ
; To set Y = 1 for accessing RAM bank 1. ; To set an immediate data 12H into Z register. ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC.
TO ACCESS DATA in RAM BANK 15 (LCD RAM)
In the RAM bank 15, this area memory can be read/written by these two access methods. Example 1: To use directly addressing mode (Through RBANK register). B0MOV MOV RBANK,#0FH A,12H ; To set RAM bank = 15 ; To move content from location 12H of RAM bank 15 to ACC
Example 2: To use indirectly addressing mode with @YZ register. MOV B0MOV B0MOV B0MOV A,#0FH Y,A Z,#12H A,@YZ
; To set Y = 15 for accessing RAM bank 15. ; To set an immediate data 12H into Z register. ; Use data pointer @YZ reads a data from RAM location 012H into ACC.
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5
SYSTEM REGISTER
OVERVIEW
The RAM area located in 80H~FFH bank 0 is system register area. The main purpose of system registers is to control peripheral hardware of the chip. Using system registers can control I/O ports, SIO, ADC, PWM, LCD, timers and counters by programming. The Memory map provides an easy and quick reference source for writing application program. To accessing these system registers is controlled by the select memory bank (RBANK = 0) or the bank 0 read/write instruction (B0MOV, B0BSET, B0BCLR...).
SYSTEM REGISTER ARRANGEMENT (BANK 0)
BYTES of SYSTEM REGISTER
SN8P1808
8 9 A B C D E F 0 L P1W P0 P0UR STK7 1 2 3 H R Z ADM ADB ADR P1M P1 P2 P3 P1UR STK7 STK6 STK6 4 Y SIOM P4M P4 P4UR STK5 5 X SIOR P5M P5 P5UR STK5
PFLAG RBANK OPTION
C D E F SIOB INTRQ INTEN OSCM LCDM P6M TC0R PCL PCH P6 T0M T0C TC0M TC0C TC1M TC1C TC1R STKP @HL @YZ STK4 STK4 STK3 STK3 STK2 STK2 STK1 STK1 STK0 STK0
6
7
8
9 -
A -
B -
Table 5-1. RAM Register Arrangement of SN8P1808 Description L, H =
Working & @HL addressing register Working and ROM address register ROM page and special flag register P3LCD and RCLK options. ADC's resolution selects register SIO mode control register SIO's data buffer Port n input/output mode register Port n data buffer Interrupts' enable register LCD mode register Timer 0 mode register Timer 0 counting register Timer/Counter 1 mode register Timer/Counter 1 counting register Stack pointer buffer RAM HL indirect addressing index pointer
X= PFLAG = OPTION= ADR = SIOM = SIOB = PnM = Pn = INTEN = LCDM= T0M = T0C = TC1M = TC1C = STKP = @HL =
R = Working register and ROM lookup data buffer Y, Z = Working, @YZ and ROM addressing register RBANK= RAM Bank Select register ADM = ADC's mode register ADB = ADC's data buffer SIOR = SIO's clock reload buffer P1W = Port 1 wakeup register PnUR = Port n pull-up register INTRQ = Interrupts' request register OSCM = Oscillator mode register PCH, PCL = Program counter TC0M = Timer/Counter 0 mode register TC0C = Timer/Counter 0 counting register TC0R = Timer/Counter 0 auto-reload data buffer TC1R = Timer/Counter 1 auto-reload data buffer STK0~STK7 = Stack 0 ~ stack 7 buffer @YZ = RAM YZ indirect addressing index pointer
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BITS of SYSTEM REGISTER
Address 080H 081H 082H 083H 084H 085H 086H 087H 088H 0B1H 0B2H 0B3H Bit7 LBIT7 HBIT7 RBIT7 ZBIT7 YBIT7 XBIT7 Bit6 LBIT6 HBIT6 RBIT6 ZBIT6 YBIT6 XBIT6 Bit5 LBIT5 HBIT5 RBIT5 ZBIT5 YBIT5 XBIT5 Bit3 Bit2 Bit1 LBIT3 LBIT2 LBIT1 HBIT3 HBIT2 HBIT1 RBIT3 RBIT2 RBIT1 ZBIT3 ZBIT2 ZBIT1 YBIT3 YBIT2 YBIT1 XBIT3 XBIT2 XBIT1 C DC RBNKS RBNKS RBNKS 3 2 1 P3LCD GCHS CHS2 CHS1 ADB8 ADB7 ADB6 ADB5 ADCKS ADB3 ADB2 ADB1 0 SRATE0 0 SCKMD SEDGE SIOR4 SIOR3 SIOR2 SIOR1 SIOB4 SIOB3 SIOB2 SIOB1 0 P13W P12W P11W 0 P13M P12M P11M P44M P43M P42M P41M P54M P53M P52M P51M P64M P63M P62M P61M T0IRQ SIOIRQ P02IRQ P01IRQ T0IEN SIOEN P02IEN P01IEN CPUM1 CPUM0 CLKMD STPHX P6HSEG LENB TC0R4 TC0R3 TC0R2 TC0R1 PC4 PC3 PC2 PC1 PC11 PC10 PC9 P04 P03 P02 P01 P13 P12 P11 P24 P23 P22 P21 P34 P33 P32 P31 P44 P43 P42 P41 P54 P53 P52 P51 P64 P63 P62 P61 T0rate0 T0C4 T0C3 T0C2 T0C1 TC0rate0 TC0CKS Aload0 TC0out TC0C4 TC0C3 TC0C2 TC0C1 TC1rate0 TC1CKS Aload1 TC1OUT TC1C4 TC1C3 TC1C2 TC1C1 TC1R4 TC1R3 TC1R2 TC1R1 STKPB3 STKPB2 STKPB1 P04R P03R P02R P01R P13R P12R P11R P44R P43R P42R P41R P54R P53R P52R P51R @HL4 @HL3 @HL2 @HL1 @YZ4 @YZ3 @YZ2 @YZ1 Bit4 LBIT4 HBIT4 RBIT4 ZBIT4 YBIT4 XBIT4 Bit0 LBIT0 HBIT0 RBIT0 ZBIT0 YBIT0 XBIT0 Z RBNKS 0 RCLK CHS0 ADB4 ADB0 TXRX SIOR0 SIOB0 P10W P10M P40M P50M P60M P00IRQ P00IEN 0 P6LSEG TC0R0 PC0 PC8 P00 P10 P20 P30 P40 P50 P60 T0TB T0C0 PWM0 TC0C0 PWM1 TC1C0 TC1R0 STKPB0 P00R P10R P40R P50R @HL0 @YZ0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W W R/W W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W R R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W W W W W R/W R/W Remarks L H R Z Y X PFLAG RBANK OPTION ADM mode register ADB data buffer ADR register SIOM mode register SIOR reload buffer SIOB data buffer P1W wakeup register P1M I/O direction P4M I/O direction P5M I/O direction P6M I/O direction INTRQ INTEN OSCM LCDM TC0R PCL PCH P0 data buffer P1 data buffer P2 data buffer P3 data buffer P4 data buffer P5 data buffer P6 data buffer T0M T0C TC0M TC0C TC1M TC1C TC1R STKP stack pointer P0UR P1UR P4UR P5UR @HL index pointer @YZ index pointer
ADENB ADS EOC ADB11 ADB10 ADB9 ADCKS ADLEN 1 0B4H SENB START SRATE1 0B5H SIOR7 SIOR6 SIOR5 0B6H SIOB7 SIOB6 SIOB5 0C0H 0 0 0 0C1H 0 0 0 0C4H P47M P46M P45M 0C5H 0 0 0 0C6H P67M P66M P65M 0C8H 0 TC1IRQ TC0IRQ 0C9H 0 TC1IEN TC0IEN 0CAH WTCKS WDRST Wdrate 0CBH BLANK 0CDH TC0R7 TC0R6 TC0R5 0CEH PC7 PC6 PC5 0CFH 0D0H P05 0D1H 0D2H P27 P26 P25 0D3H P37 P36 P35 0D4H P47 P46 P45 0D5H 0D6H P67 P66 P65 0D8H T0ENB T0rate2 T0rate1 0D9H T0C7 T0C6 T0C5 0DAH TC0ENB TC0rate2 TC0rate1 0DBH TC0C7 TC0C6 TC0C5 0DCH TC1ENB TC1rate2 TC1rate1 0DDH TC1C7 TC1C6 TC1C5 0DEH TC1R7 TC1R6 TC1R5 0DFH GIE 0E0H P05R 0E1H 0E4H P47R P46R P45R 0E5H 0E6H @HL7 @HL6 @HL5 0E7H @YZ7 @YZ6 @YZ5 (To be continued)
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Address 0F0H 0F1H 0F2H 0F3H 0F4H 0F5H 0F6H 0F7H 0F8H 0F9H 0FAH 0FBH 0FCH 0FDH 0FEH 0FFH Note:
Bit7 S7PC7 S6PC7 S5PC7 S4PC7 S3PC7 S2PC7 S1PC7 S0PC7 -
Bit6 S7PC6 S6PC6 S5PC6 S4PC6 S3PC6 S2PC6 S1PC6 S0PC6 -
Bit5 S7PC5 S6PC5 S5PC5 S4PC5 S3PC5 S2PC5 S1PC5 S0PC5 -
Bit4 S7PC4 S6PC4 S5PC4 S4PC4 S3PC4 S2PC4 S1PC4 S0PC4 -
Bit3 S7PC3 S7PC11 S6PC3 S6PC11 S5PC3 S5PC11 S4PC3 S4PC11 S3PC3 S3PC11 S2PC3 S2PC11 S1PC3 S1PC11 S0PC3 S0PC11
Bit2 S7PC2 S7PC10 S6PC2 S6PC10 S5PC2 S5PC10 S4PC2 S4PC10 S3PC2 S3PC10 S2PC2 S2PC10 S1PC2 S1PC10 S0PC2 S0PC10
Bit1 S7PC1 S7PC9 S6PC1 S6PC9 S5PC1 S5PC9 S4PC1 S4PC9 S3PC1 S3PC9 S2PC1 S2PC9 S1PC1 S1PC9 S0PC1 S0PC9
Bit0 S7PC0 S7PC8 S6PC0 S6PC8 S5PC0 S5PC8 S4PC0 S4PC8 S3PC0 S3PC8 S2PC0 S2PC8 S1PC0 S1PC8 S0PC0 S0PC8
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Remarks STK7L STK7H STK6L STK6H STK5L STK5H STK4L STK4H STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H
Table 5-2. Bit System Register Table of SN8P1808 a). All of register names had been declared in SN8ASM assembler. b). One-bit name had been declared in SN8ASM assembler with "F" prefix code. c). It will get logic "H" data, when use instruction to check empty location. d). The low nibble of ADR register is read only. e). "b0bset", "b0bclr", "bset", "bclr" of instructions just only support "R/W" registers. f). For detail description please refer file of "System Register Quick Reference Table"
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6
POWER ON RESET
OVERVIEW
SN8P1800 provides two system resets. One is external reset and the other is low voltage detector (LVD). The external reset is a simple RC circuit connecting to the reset pin. The low voltage detector (LVD) is built in internal circuit. When one of the reset devices occurs, the system will reset and the system registers become initial value. The timing diagram is as following.
VDD
LVD Detect Level
External Reset
External Reset Detect Level
LVD
End of LVD Reset
Internal Reset Signal
End of External Reset
Figure 6-1 Power on Reset Timing Diagram
Notice : The working current of the LVD is about 100uA.
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EXTERNAL RESET DESCRIPTION
The external reset is a low level active device. The reset pin receives the low voltage and resets the system. When the voltage detects high level, it stops resetting the system. Users can use an external reset circuit to control system operation. It is necessary that the VDD must be stable.
VDD
External Reset
External Reset Detect Level
Internal Reset Signal
System Reset
End of External Reset
Figure 6-2 External Reset Timing Diagram
Users must to be sure the VDD stable earlier than external reset (Figure 5-2) or the external reset will fail. The external reset circuit is a simple RC circuit as following.
R 20K ohm
VDD RST
C 0.1uF VSS
MCU
VCC
GND
Figure 6-3. External Reset Circuit
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In worse-power condition as brown out reset. The reset pin may keep high level but the VDD is low voltage. That makes the system reset fail and chip error. To connect a diode from reset pin to VDD is a good solution. The circuit can force the capacitor to release electric charge and drop the voltage, and solve the error.
DIODE
R 20K ohm
VDD RST
C 0.1uF VSS
MCU
VCC
GND
Figure 6-4. External Reset Circuit with Diode
LOW VOLTAGE DETECTOR (LVD) DESCRIPTION
The LVD is a low voltage detector. It detects VDD level and reset the system as the VDD lower than the desired voltage. The detect level is 2.4V. If the VDD lower than 2.4V, the system resets. The LVD function is controlled by code option. Users can turn on it for special application like worse power condition. LVD work with external reset function. They are OR active.
VDD
LVD Detect Level
LVD
System Reset
End of LVD Reset
Figure 6-5. LVD Timing Diagram The LVD can protect system to work well under brownout reset. But it is a high consumptive circuit. In 3V condition, the LVD consumes about 100uA. It is a very large consumption for battery system. So the LVD supports AC system well.
Notice: LVD is selected by code option.
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7
OSCILLATORS
OVERVIEW
The SN8P1800 highly performs the dual clock micro-controller system. The dual clocks are high-speed clock and low-speed clock. The high-speed clock frequency is supplied through the external oscillator circuit. The low-speed clock frequency is supplied through external low clock oscillator (32.768K) by crystal or RC mode. Because Real-Time-Clock (RTC) used low-speed clock for timer, 32768Hz X'tal usually used for low-speed clock to an exact Real-Time-Clock. The external high-speed clock and the external low-speed clock can be system clock (Fosc). And the system clock is divided by 4 to be the instruction cycle (Fcpu).
Fcpu = Fosc / 4
The system clock is required by the following peripheral modules: Basic timer (T0) Timer counter 0 (TC0) Timer counter 1 (TC1) Watchdog timer Serial I/O interface (SIO) AD converter PWM output (PWM0, PWM1) Buzzer output (TC0OUT, TC1OUT)
CLOCK BLOCK DIAGRAM
HXRC(1:0) is code option *00= RC *01 =32 Khz Oscillator *10 = High Speed Oscillator (>10Mhz) *11 = Standard Oscillator (4Mhz) STPHX XIN XOUT CPUM0 LXOSC. CPUM0 fl HXRC OSG
Divided by 2 1 : Disable 0 : Enable
CLKMD
fosc/4
CPUM0
HXOSC. fh
Divided by 2
Divided by 4
fcpu
OSG : Oscillator Safe Guard 1 : Disable -- System Default 0 : Enable
Figure 7-1. Clock Block Diagram HXOSC: External high-speed clock. LXOSC: External low-speed clock. OSG: Oscillator safe guard.
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OSCM REGISTER DESCRIPTION
The OSCM register is a oscillator control register. It can control oscillator select, system mode, watchdog timer clock source and rate.
OSCM initial value = 0000 000x 0CAH OSCM Bit 7 WTCKS R/W Bit 6 WDRST R/W Bit 5 Wdrate R/W Bit 4 CPUM1 R/W Bit 3 CPUM0 R/W Bit 2 CLKMD R/W Bit 1 STPHX R/W Bit 0 -
STPHX: Eternal high-speed oscillator control bit. 0 = free run, 1 = stop. This bit just only controls external high-speed oscillator. If STPHX=1, the external low-speed RC oscillator is still running. CLKMD: System high/Low speed mode select bit. 0 = normal (dual) mode, 1 = slow mode. CPUM1,CPUM0: CPU operating mode control bit. 00=normal, 01= sleep (power down) mode to turn off both high/low clock, 10=green mode, 11=reserved WTCKS: Watchdog clock source select bit. 0 = fcpu, 1 = internal RC low clock.
OPTION REGISTER DESCRIPTION
OPTION initial value = xxxx xx00 088H OPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 P3LCD R/W Bit 0 RCLK R/W
RCLK: External low oscillator type control bit. 0 = Crystal mode , 1 = RC mode. P3LCD: P3 I/O function control bit. 0 = LCD segment, 1 = input mode with pull-up resistor..
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EXTERNAL HIGH-SPEED OSCILLATOR
SN8P1800 can be operated in four different oscillator modes. There are external RC oscillator modes, high crystal/resonator mode (12M code option), standard crystal/resonator mode (4M code option) and low crystal mode (32K code option). For different application, the users can select one of satiable oscillator mode by programming code option to generate system high-speed clock source after reset.
Example: Stop external high-speed oscillator. B0BSET FSTPHX ; To stop external high-speed oscillator only.
B0BSET
FCPUM0
; To stop external high-speed oscillator and external low-speed ; oscillator called power down mode (sleep mode).
OSCILLATOR MODE CODE OPTION
SN8P1800 has four oscillator modes for different applications. These modes are 4M, 12M, 32K and RC. The main purpose is to support different oscillator types and frequencies. High-speed crystal needs more current but the low one doesn't. For crystals, there are three steps to select. If the oscillator is RC type, to select "RC" and the system will divide the frequency by 2 automatically. User can select oscillator mode from Code Option table before compiling. The table is as follow.
Code Option 00 01 10 11
Oscillator Mode RC mode 32K 12M 4M
Remark Output the Fcpu square wave from Xout pin. 32768Hz 12MHz ~ 16MHz 3.58MHz
OSCILLATOR DEVIDE BY 2 CODE OPTION
SN8P1800 has an external clock divide by 2 function. It is a code option called "High_Clk / 2". If "High_Clk / 2" is enabled, the external clock frequency is divided by 8 for the Fcpu. Fcpu is equal to Fosc/8. If "High_Clk / 2" is disabled, the external clock frequency is divided by 4 for the Fcpu. The Fcpu is equal to Fosc/4. Note: In RC mode, "High_Clk / 2" is always enabled.
OSCILLATOR SAFE GUARD CODE OPTION
SN8P1800 builds in an oscillator safe guard (OSG) to make oscillator more stable. It is a low-pass filter circuit and stops high frequency noise into system from external oscillator circuit. This function makes system to work better under AC noisy conditions.
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SYSTEM OSCILLATOR CIRCUITS
20PF VDD XIN CRYSTAL 20PF XOUT VSS
MCU
Figure 7-2. Crystal/Ceramic Oscillator
R
VDD XIN
C
XOUT VSS
MCU
Figure 7-3. RC Oscillator
External Clock Input
VDD XIN XOUT VSS
MCU
Figure 7-4. External clock input Note1: The VDD and VSS of external oscillator circuit must be from micro-controller. Don't connect them from power terminal. Note2: The external clock input mode can select RC type oscillator or crystal type oscillator of the code option and input the external clock into XIN pin. Note3: In RC type oscillator code option situation, the external clock's frequency is divided by 2. Note4: The power and ground of external oscillator circuit must be connected from the micro-controller's VDD and VSS. It is necessary to step up the performance of the whole system.
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External RC Oscillator Frequency Measurement
There are two ways to get the Fosc frequency of external RC oscillator. One measures the XOUT output waveform. Under external RC oscillator mode, the XOUT outputs the square waveform whose frequency is Fcpu. The other measures the external RC frequency by instruction cycle (Fcpu). The external RC frequency is the Fcpu multiplied by 4. We can get the Fosc frequency of external RC from the Fcpu frequency. The sub-routine to get Fcpu frequency of external oscillator is as the following.
Example: Fcpu instruction cycle of external oscillator B0BSET P1M.0 ; Set P1.0 to be output mode for outputting Fcpu toggle signal.
@@: B0BSET B0BCLR JMP P1.0 P1.0 @B ; Output Fcpu toggle signal in low-speed clock mode. ; Measure the Fcpu frequency by oscilloscope.
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SYSTEM MODE DESCRIPTION
OVERVIEW
The chip is featured with low power consumption by switching around three different modes as following.
High-speed mode Low-speed mode Power-down mode (Sleep mode) Green mode
In actual application, the user can adjust the chip's controller to work in these four modes by using OSCM register. At the high-speed mode, the instruction cycle (Fcpu) is Fosc/4. At the low-speed mode and 3V, the Fcpu is 16KHz/4.
NORMAL MODE
In normal mode, the system clock source is external high-speed clock. After power on, the system works under normal mode. The instruction cycle is fosc/4. When the external high-speed oscillator is 3.58MHz, the instruction cycle is 3.58MHz/4 = 895KHz. All software and hardware are executed and working. In normal mode, system can get into power down mode, slow mode and green mode.
SLOW MODE
In slow mode, the system clock source is external low-speed RC clock. To set CLKMD = 1, the system switches into slow mode. In slow mode, the system works as normal mode but the clock slower. The system in slow mode can get into normal mode, power down mode and green mode. To set STPHX = 1 to stop the external high-speed oscillator, and then the system consumes less power.
GREEN MODE
The green mode is a less power consumption mode. Under green mode, there are only T0 still counting and the other hardware stopping. The external high-speed oscillator or external low-speed oscillator is operating. To set CPUM1 = 1 and CPUM0 = 0, the system gets into green mode. The system can be waked up to last system mode by T0 timer timeout and P0, P1 trigger signal. The green mode provides a time-variable wakeup function. Users can decide wakeup time by setting T0 timer. There are two channels into green mode. One is normal mode and the other is slow mode. In normal mode, the T0 timers overflow time is very short. In slow mode, the overflow time is longer. Users can select appropriate situation for their applications. Under green mode, the power consumption is 5u amp in 3V condition.
POWER DOWN MODE
The power down mode is also called sleep mode. The chip stops working as sleeping status. The power consumption is very less almost to zero. The power down mode is usually applied to low power consuming system as battery power productions. To set CUPM0 = 1, the system gets into power down mode. The external high-speed and low-speed oscillators are turned off. The system can be waked up by P0, P1 trigger signal.
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SYSTEM MODE CONTROL
SN8P1800 SYSTEM MODE BLOCK DIAGRAM
Power Down Mode (Sleep Mode)
P0, P1 wake-up function active. External reset circuit active. CPUM1, CPUM0 = 01
CLKMD = 1
Normal Mode
CLKMD = 0
Slow Mode
P0, P1 wake-up function active. T0, TC0 time out. External reset circuit active.
CPUM1, CPUM0 = 10
P0, P1 wake-up function active. T0, TC0 time out.
Green Mode
External reset circuit active.
Figure 7-5. SN8P1800 System Mode Block Diagram
MODE HX osc. LX osc. CPU instruction T0 timer TC0 timer TC1 timer Watchdog timer Internal interrupt External interrupt Wakeup source
NORMAL Running Running Executing *Active *Active *Active Active All active All active -
SLOW By STPHX Running Executing *Active *Active *Active Active All active All active -
Green By STPHX Running Stop *Active *Active Inactive Inactive TC0 All Active Port0, Port1, T0, Reset
SLEEP Stop Stop Stop Inactive Inactive Inactive Inactive All inactive All inactive P0, P1, Reset
REMARK
* Active by program
Table 7-1. Oscillator Operating Mode Description
Note: In the green mode, T0 trigger signals can switch CPU return to the last mode. If the system was into green mode from normal mode, the system returns to normal mode. If the system was into green mode from slow mode, the system returns to slow mode.
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SYSTEM MODE SWITCHING
Normal/Slow mode to power down (sleep) mode. CPUM0 = 1) B0BSET FCPUM0 ; Set CPUM0 = 1.
Note: In normal mode and slow mode, the CPUM1 = 0 and can omit to set CPUM1 = 0 routine. Normal mode to slow mode. B0BSET B0BSET FCLKMD FSTPHX ;To set CLKMD = 1 ;To stop external high-speed oscillator.
Note: To stop high-speed oscillator is not necessary and user can omit it. Switch slow mode to normal mode (The external high-speed oscillator is still running) B0BCLR FCLKMD ;To set CLKMD = 0
Switch slow mode to normal mode (The external high-speed oscillator stops) If external high clock stop and program want to switch back normal mode. It is necessary to delay at least 10mS for external clock stable. B0BCLR B0MOV DECMS JMP B0BCLR FSTPHX Z, #27 Z @B FCLKMD ; Turn on the external high-speed oscillator. ; If VDD = 5V, internal RC=32KHz (typical) will delay ; 0.125ms X 81 = 10.125ms for external clock stable ; ; Change the system back to the normal mode
@@:
Normal/Slow mode to green mode. CPUM1, CPUM0 = 10 System can return to the last mode by P0, P1 and T0 wakeup function. Example: Go into Green mode. B0BSET FCPUM1 ; To set CPUM1, CPUM0 = 10
Note: In normal mode or slow mode, the CPUM0 = 0 and can omit to set CPUM0 = 0 routine. Example: Go into Green mode and enable T0 wakeup function. ; Set T0 timer wakeup functon. B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BCLR B0BCLR B0BSET ; Go into green mode B0BCLR B0BSET
FT0IEN FT0ENB A,#20H T0M,A A,#74H T0C,A FT0IEN FT0IRQ FT0ENB FCPUM0 FCPUM1
; To disable T0 interrupt service ; To disable T0 timer ; ; To set T0 clock = fcpu / 64 ; To set T0C initial value = 74H (To set T0 interval = 10 ms) ; To disable T0 interrupt service ; To clear T0 interrupt request ; To enable T0 timer ;To set CPUMx = 10
Note: If T0ENB = 0, T0 is without wakeup from green mode to normal/slow mode function.
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WAKEUP TIME
OVERVIEW
The external high-speed oscillator needs a delay time from stopping to operating. The delay is very necessary and makes the oscillator to work stably. Some conditions during system operating, the external high-speed oscillator often runs and stops. Under these condition, the delay time for external high-speed oscillator restart is called wakeup time. There are two conditions need wakeup time. One is power down mode to normal mode. The other one is slow mode to normal mode. For the first case, SN8P1800 provides 2048 oscillator clocks to be the wakeup time. But in the last case, users need to make the wakeup time by themselves.
HARDWARE WAKEUP
When the system is in power down mode (sleep mode), the external high-speed oscillator stops. For wakeup into normal, SN8P1800 provides 2048 external high-speed oscillator clocks to be the wakeup time for warming up the oscillator circuit. After the wakeup time, the system goes into the normal mode. The value of the wakeup time is as following.
The wakeup time = 1/Fosc * 2048 (sec)
Example: In power down mode (sleep mode), the system is waked up by P0 or P1 trigger signal. After the wakeup time, the system goes into normal mode. The wakeup time of P0, P1 wakeup function is as following.
The wakeup time = 1/Fosc * 2048 = 0.57 ms The wakeup time = 1/Fosc * 2048 = 62.5 ms
(Fosc = 3.58MHz) (Fosc=32768Hz)
Under power down mode (sleep mode), there are only I/O ports with wakeup function making the system to return normal mode. The Port 0 and Port 1 have wakeup function. Port 0's wakeup function always enables. The Port 1 controls by the P1W register.
P1W initial value = xx00 0000 0C0H P1W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 P13W W Bit 2 P12W W Bit 1 P11W W Bit 0 P10W W
P10W~P13W: Port 1 wakeup function control bits. 0 = none wakeup function, 1 = Enable each pin of Port 1 wakeup function.
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8
TIMERS COUNTERS
WATCHDOG TIMER (WDT)
The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program get into the unknown status by noise interference, WDT's overflow signal will reset this chip and restart operation. The instruction that clear the watch-dog timer (B0BSET FWDRST) should be executed at proper points in a program within a given period. If an instruction that clears the watchdog timer is not executed within the period and the watchdog timer overflows, reset signal is generated and system is restarted with reset status. In order to generate different output timings, the user can control watchdog timer by modifying Wdrate control bits of OSCM register. The watchdog timer will be disabled at green and power down modes.
OSCM initial value = 0000 000x 0CAH OSCM Bit 7 WTCKS R/W Bit 6 WDRST R/W Bit 5 Wdrate R/W Bit 4 CPUM1 R/W Bit 3 CPUM0 R/W Bit 2 CLKMD R/W Bit 1 STPHX R/W Bit 0 0 -
Wdrate: Watchdog timer rate select bit. 0 =14th, 1 = 8th. WDRST : Watch dog timer reset bit. 0 = Non reset, 1 = clear the watchdog timer's counter. WTCKS: Watchdog clock source select bit. 0 = Fcpu, 1 = internal RC low clock.
WTCKS 0 0 0 0 1
WTRATE 0 1 0 1 -
CLKMD 0 0 1 1 -
Watchdog Timer Overflow Time 1 / ( fcpu / 214 / 16 ) = 293 ms, Fosc=3.58MHz 1 / ( fcpu / 28 / 16 ) = 500 ms, Fosc=32768Hz 1 / ( fcpu / 214 / 16 ) = 32s, Fosc=32768Hz 1 / ( fcpu / 28 / 16 ) = 500ms, Fosc=32768Hz 1 / ( 32768 / 512 / 16 ) ~ 0.25s
Figure 8-1. Watchdog timer overflow time table Note: The watch dog timer can be enabled or disabled by the code option.
Example: An operation of watch-dog timer is as following. To clear the watchdog timer's counter in the top of the main routine of the program. Main: B0BSET . CALL CALL . . . JMP FWDRST . SUB1 SUB2 . . . MAIN ; Clear the watchdog timer's counter.
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BASIC TIMER 0 ( T0 )
OVERVIEW
The basic timer (T0) is an 8-bit binary up counter. It uses T0M register to select T0C's input clock for counting a precision time. If the T0 timer has occur an overflow (from FFH to 00H), it will continue counting and issue a time-out signal to trigger T0 interrupt to request interrupt service. The main purposes of the T0 basic timer is as following. 8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock frequency.
T0enb
Internal data bus pre_load
fcpu
/2(8-T0Rate)
T0C 8-bit binary counter
T0 Time out
Figure 8-2. Basic Timer T0 Block Diagram
T0M REGISTER DESCRIPTION
The T0M is the basic timer mode register which is a 8-bit read/write register and only used the high nibble. By loading different value into the T0M register, users can modify the basic timer clock dynamically as program executing. Eight rates for T0 timer can be selected by T0RATE0 ~ T0RATE2 bits. The range is from fcpu/2 to fcpu/256. The T0M initial value is zero and the rate is fcpu/256. The bit7 of T0M called T0ENB is the control bit to start T0 timer. The combination of these bits is to determine the T0 timer clock frequency and the intervals. T0M initial value = 0000 xxxx 0D8H T0M Bit 7 T0ENB R/W Bit 6 T0RATE2 R/W Bit 5 T0RATE1 R/W Bit 4 T0RATE0 R/W Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 T0TB R/W
T0ENB: T0 timer control bit. 0 = disable, 1 = enable. T0RATE2~T0RATE0: The T0 timer's clock source select bits. 000 = fcpu/256, 001 = fcpu/128, ... , 110 = fcpu/4, 111 = fcpu/2. T0TB : Timer 0 as the Real-Time clock time base. 0 = Timer 0 function as a normal timer system. 1 = Timer 0 function as a Real-Time Clock. The clock source of timer 0 will be switched to external low clock (32.768K crystal oscillator).
Note: 1. Register setting for Timer 0 as Real-Timer clock: Register Bit OPTION RCLK T0M T0TB Logic Description 0 External low oscillator type = Crystal mode 1 Timer 0 function = Real-Time Clock
Note:2. Interrupt/Wakeup period of Real-Time clock is 0.5 second in 32768hz X'tal. (32768hz / 64 / 256 = 2 hz).
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T0C COUNTING REGISTER
T0C is an 8-bit counter register for the basic timer (T0). T0C must be reset whenever the T0ENB is set "1" to start the basic timer. T0C is incremented by one with every clock pulse which frequency is determined by T0RATE0 ~ T0RATE2. When T0C has incremented to "0FFH", it will be cleared to "00H" in next clock and an overflow generated. Under T0 interrupt service request (T0IEN) enable condition, the T0 interrupt request flag will be set "1" and the system executes the interrupt service routine. The T0C has no auto reload function. After T0C overflow, the T0C is continuing counting. Users need to reset T0C value to get a accurate time. T0C initial value = xxxx xxxx 0D9H T0C Bit 7 T0C7 R/W Bit 6 T0C6 R/W Bit 5 T0C5 R/W Bit 4 T0C4 R/W Bit 3 T0C3 R/W Bit 2 T0C2 R/W Bit 1 T0C1 R/W Bit 0 T0C0 R/W
T0RATE 000 001 010 011 100 101 110 111
T0CLOCK fcpu/256 fcpu/128 fcpu/64 fcpu/32 fcpu/16 fcpu/8 fcpu/4 fcpu/2
High speed mode (fcpu = 3.58MHz / 4) Max overflow interval One step = max/256 73.2 ms 286us 36.6 ms 143us 18.3 ms 71.5us 9.15 ms 35.8us 4.57 ms 17.9us 2.28 ms 8.94us 1.14 ms 4.47us 0.57 ms 2.23us
Low speed mode (fcpu = 32768Hz / 4) Max overflow interval One step = max/256 8000 ms 31.25 ms 4000 ms 15.63 ms 2000 ms 7.8 ms 1000 ms 3.9 ms 500 ms 1.95 ms 250 ms 0.98 ms 125 ms 0.49 ms 62.5 ms 0.24 ms
Figure 8-3. The Timing Table of Basic Timer T0. The equation of T0C initial value is as following. T0C initial value = 256 - (T0 interrupt interval time * input clock)
Example : To set 10ms interval time for T0 interrupt at 3.58MHz high-speed mode. T0C value (74H) = 256 (10ms * fcpu/64) T0C initial value = 256 - (T0 interrupt interval time * input clock) = 256 - (10ms * 3.58 * 106 / 4 / 64) = 256 - (10-2 * 3.58 * 106 / 4 / 64) = 116 = 74H
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T0 BASIC TIMER OPERATION SEQUENCE
The T0 basic timer's sequence of operation can be following. Set the T0C initial value to setup the interval time. Set the T0ENB to be "1" to enable T0 basic timer. T0C is incremented by one with each clock pulse which frequency is corresponding to T0M selection. T0C overflow when T0C from FFH to 00H. When T0C overflow occur, the T0IRQ flag is set to be "1" by hardware. Execute the interrupt service routine. Users reset the T0C value and resume the T0 timer operation.
Example: Setup the T0M and T0C. B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET FT0IEN FT0ENB A,#20H T0M,A A,#74H T0C,A FT0IEN FT0IRQ FT0ENB ; To disable T0 interrupt service ; To disable T0 timer ; ; To set T0 clock = fcpu / 64 ; To set T0C initial value = 74H (To set T0 interval = 10 ms) ; To enable T0 interrupt service ; To clear T0 interrupt request ; To enable T0 timer
Example: T0 interrupt service routine. ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR MOV B0MOV . . JMP . . EXIT_INT: POP B0XCH RETI ; POP ; Restore ACC value. ; Exit interrupt vector A, ACCBUF ; Store ACC value. ; Push ; Check T0IRQ ; T0IRQ = 0, exit interrupt vector ; Reset T0IRQ ; Reload T0C ; T0 interrupt service routine ; End of T0 interrupt service routine and exit interrupt vector 8 INT_SERVICE ; Interrupt vector
FT0IRQ EXIT_INT FT0IRQ A,#74H T0C,A . . EXIT_INT . .
A, ACCBUF
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TIMER COUNTER 0 (TC0)
OVERVIEW
The timer counter 0 (TC0) is used to generate an interrupt request when a specified time interval has elapsed. TC0 has a auto re-loadable counter that consists of two parts: an 8-bit reload register (TC0R) into which you write the
Aload0 TC0R reload data buffer
Internal P5.4 I/O circuit
Buzzer
TC0out
Auto. reload
O 2
P5.4
R Compare
PWM PWM0OUT
TC0enb load
S
fcpu
/ 2(8-TC0Rate)
CPUM0
TC0C 8-bit binary counter
TC0 Time out
counter reference value, and an 8-bit counter register (TC0C) whose value is automatically incremented by counter logic. Figure 8-4. Timer Count TC0 Block Diagram The main purposes of the TC0 timer counter is as following.
8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock frequency. Arbitrary frequency output (Buzzer output): Outputs selectable clock frequencies to the BZ0 pin (P5.4). PWM function: PWM output can be generated by the PWM1OUT bit and output to PWM0OUT pin (P5.4).
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TC0M MODE REGISTER
The TC0M is the timer counter mode register, which is an 8-bit read/write register. By loading different value into the TC0M register, users can modify the timer counter clock frequency dynamically when program executing. Eight rates for TC0 timer can be selected by TC0RATE0 ~ TC0RATE2 bits. The range is from fcpu/2 to fcpu/256. The TC0M initial value is zero and the rate is fcpu/256. The bit7 of TC0M called TC0ENB is the control bit to start TC0 timer. The combination of these bits is to determine the TC0 timer clock frequency and the intervals.
TC0M initial value = 0000 0000
0DAH TC0M
Bit 7 TC0ENB R/W
Bit 6 Bit 5 Bit 4 TC0RATE2 TC0RATE1 TC0RATE0 R/W R/W R/W
Bit 3 TC0CKS R/W
Bit 2 ALOAD0 R/W
Bit 1 TC0OUT R/W
Bit 0 PWM0OUT R/W
TC0ENB: TC0 counter/BZ0/PWM0OUT enable bit. 0 = disable, 1 = enable. TC0RATE2~TC0RATE0: TC0 internal clock select bits. 000 = fcpu/256, 001 = fcpu/128, ... , 110 = fcpu/4, 111 = fcpu/2. TC0CKS: TC0 clock source select bit. "0" = Fcpu, "1" = External clock come from INT0/P0.0 pin. TC0 will be an event counter. ALOAD0: TC0 auto-reload function control bit. 0 = none auto-reload, 1 = auto-reload. TC0OUT: TC0 time-out toggle signal output control bit. 0 = To disable TC0 signal output and to enable P5.4's I/O function, 1 = To enable TC0's signal output and to disable P5.4's I/O function. (Auto-disable the PWM0OUT function.) PWM0OUT: TC0's PWM output control bit. 0 = To disable the PWM output, 1 = To enable the PWM output (The TC0OUT control bit must = 0 )
Note1: When TC0CKS=1, TC0 became an external event counter. No more P0.0 interrupt request will be raised. (P0.0IRQ will be always 0) Note2: The ICE S8KC do not support the PWM0OUT and TC0OUT Function. The PWM0OUT and TC0OUT must use the S8KD ICE (or later) to verify the function.
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TC0C COUNTING REGISTER
TC0C is an 8-bit counter register for the timer counter (TC0). TC0C must be reset whenever the TC0ENB is set "1" to start the timer counter. TC0C is incremented by one with a clock pulse which the frequency is determined by TC0RATE0 ~ TC0RATE2. When TC0C has incremented to "0FFH", it is will be cleared to "00H" in next clock and an overflow is generated. Under TC0 interrupt service request (TC0IEN) enable condition, the TC0 interrupt request flag will be set "1" and the system executes the interrupt service routine.
TC0C initial value = xxxx xxxx
0DBH TC0C
Bit 7 TC0C7 R/W
Bit 6 TC0C6 R/W
Bit 5 TC0C5 R/W
Bit 4 TC0C4 R/W
Bit 3 TC0C3 R/W
Bit 2 TC0C2 R/W
Bit 1 TC0C1 R/W
Bit 0 TC0C0 R/W
TC0RATE TC0CLOCK 000 001 010 011 100 101 110 111 fcpu/256 fcpu/128 fcpu/64 fcpu/32 fcpu/16 fcpu/8 fcpu/4 fcpu/2
High speed mode (fcpu = 3.58MHz / 4) Max overflow interval One step = max/256 73.2 ms 286us 36.6 ms 143us 18.3 ms 71.5us 9.15 ms 35.8us 4.57 ms 17.9us 2.28 ms 8.94us 1.14 ms 4.47us 0.57 ms 2.23us
Low speed mode (fcpu = 32768Hz / 4) Max overflow interval One step = max/256 8000 ms 31.25 ms 4000 ms 15.63 ms 2000 ms 7.8 ms 1000 ms 3.9 ms 500 ms 1.95 ms 250 ms 0.98 ms 125 ms 0.49 ms 62.5 ms 0.24 ms
Table 8-1. The Timing Table of Timer Count TC0
The equation of TC0C initial value is as following.
TC0C initial value = 256 - (TC0 interrupt interval time * input clock)
Example: To set 10ms interval time for TC0 interrupt at 3.58MHz high-speed mode. TC0C value (74H) = 256 - (10ms * fcpu/64) TC0C initial value = 256 - (TC0 interrupt interval time * input clock) = 256 - (10ms * 3.58 * 106 / 4 / 64) = 256 - (10-2 * 3.58 * 106 / 4 / 64) = 116 = 74H
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TC0R AUTO-LOAD REGISTER
TC0R is an 8-bit register for the TC0 auto-reload function. TC0R's value applies to TC0OUT and PWM0OUT functions.. Under TC0OUT application, users must enable and set the TC0R register. The main purpose of TC0R is as following. Store the auto-reload value and set into TC0C when the TC0C overflow. (ALOAD0 = 1). Store the duty value of PWM0OUT function.
TC0R initial value = xxxx xxxx
0CDH TC0R
Bit 7 TC0R7 W
Bit 6 TC0R6 W
Bit 5 TC0R5 W
Bit 4 TC0R4 W
Bit 3 TC0R3 W
Bit 2 TC0R2 W
Bit 1 TC0R1 W
Bit 0 TC0R0 W
The equation of TC0R initial value is like TC0C as following.
TC0R initial value = 256 - (TC0 interrupt interval time * input clock)
Note: The TC0R is write-only register can't be process by INCMS, DECMS instructions.
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TC0 TIMER COUNTER OPERATION SEQUENCE
The TC0 timer counter's sequence of operation can be following. Set the TC0C initial value to setup the interval time. Set the TC0ENB to be "1" to enable TC0 timer counter. TC0C is incremented by one with each clock pulse which frequency is corresponding to T0M selection. TC0C overflow when TC0C from FFH to 00H. When TC0C overflow occur, the TC0IRQ flag is set to be "1" by hardware. Execute the interrupt service routine. Users reset the TC0C value and resume the TC0 timer operation.
Example: Setup the TC0M and TC0C without auto-reload function.
B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET
FTC0IEN FTC0ENB A,#20H TC0M,A A,#74H TC0C,A FTC0IEN FTC0IRQ FTC0ENB
; To disable TC0 interrupt service ; To disable TC0 timer ; ; To set TC0 clock = fcpu / 64 ; To set TC0C initial value = 74H ;(To set TC0 interval = 10 ms) ; To enable TC0 interrupt service ; To clear TC0 interrupt request ; To enable TC0 timer
Example: Setup the TC0M and TC0C with auto-reload function.
B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0MOV B0BSET B0BCLR B0BSET B0BSET
FTC0IEN FTC0ENB A,#20H TC0M,A A,#74H TC0C,A TC0R,A FTC0IEN FTC0IRQ FTC0ENB ALOAD0
; To disable TC0 interrupt service ; To disable TC0 timer ; ; To set TC0 clock = fcpu / 64 ; To set TC0C initial value = 74H ; (To set TC0 interval = 10 ms) ; To set TC0R auto-reload register ; To enable TC0 interrupt service ; To clear TC0 interrupt request ; To enable TC0 timer ; To enable TC0 auto-reload function.
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Example: TC0 interrupt service routine without auto-reload function.
ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR MOV B0MOV . . JMP . . EXIT_INT: POP B0XCH RETI
8 INT_SERVICE
; Interrupt vector
A, ACCBUF
; B0XCH doesn't change C, Z flag ; Push ; Check TC0IRQ ; TC0IRQ = 0, exit interrupt vector ; Reset TC0IRQ ; Reload TC0C ; TC0 interrupt service routine ; End of TC0 interrupt service routine and exit interrupt vector
FTC0IRQ EXIT_INT FTC0IRQ A,#74H TC0C,A . . EXIT_INT . .
A, ACCBUF
; Pop ; Restore ACC value. ; Exit interrupt vector
Example: TC0 interrupt service routine with auto-reload.
ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR . . JMP . . EXIT_INT: POP B0XCH RETI
8 INT_SERVICE
; Interrupt vector
A, ACCBUF
; B0XCH doesn't change C, Z flag ; Push ; Check TC0IRQ ; TC0IRQ = 0, exit interrupt vector ; Reset TC0IRQ ; TC0 interrupt service routine ; End of TC0 interrupt service routine and exit interrupt vector
FTC0IRQ EXIT_INT FTC0IRQ . . EXIT_INT . .
A, ACCBUF
; Pop ; Restore ACC value. ; Exit interrupt vector
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TC0 CLOCK FREQUENCY OUTPUT (BUZZER)
TC0 timer counter provides a frequency output function. By setting the TC0 clock frequency, the clock signal is output to P5.4 and the P5.4 general purpose I/O function is auto-disable. The TC0 output signal divides by 2. The TC0 clock has many combinations and easily to make difference frequency. This function applies as buzzer output to output multi-frequency.
Figure 8-5. The TC0OUT Pulse Frequency
Example: Setup TC0OUT output from TC0 to TC0OUT (P5.4). The external high-speed clock is 4MHz. The TC0OUT frequency is 1KHz. Because the TC0OUT signal is divided by 2, set the TC0 clock to 2KHz. The TC0 clock source is from external oscillator clock. T0C rate is Fcpu/4. The TC0RATE2~TC0RATE1 = 110. TC0C = TC0R = 131.
MOV B0MOV MOV B0MOV B0MOV B0BSET B0BSET B0BSET
A,#01100000B TC0M,A A,#131 TC0C,A TC0R,A FTC0OUT FALOAD0 FTC0ENB
; Set the TC0 rate to Fcpu/4 ; Set the auto-reload reference value
; Enable TC0 output to P5.4 and disable P5.4 I/O function ; Enable TC0 auto-reload function ; Enable TC0 timer
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TC0OUT FREQUENCY TABLE
Fosc = 4MHz, TC0 Rate = Fcpu/8
TC0R TC0OUT (KHz) 0.2441 0.2451 0.2461 0.2470 0.2480 0.2490 0.2500 0.2510 0.2520 0.2530 0.2541 0.2551 0.2561 0.2572 0.2583 0.2593 0.2604 0.2615 0.2626 0.2637 0.2648 0.2660 0.2671 0.2682 0.2694 0.2706 0.2717 0.2729 0.2741 0.2753 0.2765 0.2778 0.2790 0.2803 0.2815 0.2828 0.2841 0.2854 0.2867 0.2880 0.2894 0.2907 0.2921 0.2934 0.2948 0.2962 0.2976 0.2990 0.3005 0.3019 0.3034 0.3049 0.3064 0.3079 0.3094 0.3109 TC0R TC0OUT (KHz) 0.3125 0.3141 0.3157 0.3173 0.3189 0.3205 0.3222 0.3238 0.3255 0.3272 0.3289 0.3307 0.3324 0.3342 0.3360 0.3378 0.3397 0.3415 0.3434 0.3453 0.3472 0.3492 0.3511 0.3531 0.3551 0.3571 0.3592 0.3613 0.3634 0.3655 0.3676 0.3698 0.3720 0.3743 0.3765 0.3788 0.3811 0.3834 0.3858 0.3882 0.3906 0.3931 0.3956 0.3981 0.4006 0.4032 0.4058 0.4085 0.4112 0.4139 0.4167 0.4195 0.4223 0.4252 0.4281 0.4310 TC0R TC0OUT (KHz) 0.4340 0.4371 0.4401 0.4433 0.4464 0.4496 0.4529 0.4562 0.4596 0.4630 0.4664 0.4699 0.4735 0.4771 0.4808 0.4845 0.4883 0.4921 0.4960 0.5000 0.5040 0.5081 0.5123 0.5165 0.5208 0.5252 0.5297 0.5342 0.5388 0.5435 0.5482 0.5531 0.5580 0.5631 0.5682 0.5734 0.5787 0.5841 0.5896 0.5952 0.6010 0.6068 0.6127 0.6188 0.6250 0.6313 0.6378 0.6443 0.6510 0.6579 0.6649 0.6720 0.6793 0.6868 0.6944 0.7022 TC0R TC0OUT (KHz) 0.7102 0.7184 0.7267 0.7353 0.7440 0.7530 0.7622 0.7716 0.7813 0.7911 0.8013 0.8117 0.8224 0.8333 0.8446 0.8562 0.8681 0.8803 0.8929 0.9058 0.9191 0.9328 0.9470 0.9615 0.9766 0.9921 1.0081 1.0246 1.0417 1.0593 1.0776 1.0965 1.1161 1.1364 1.1574 1.1792 1.2019 1.2255 1.2500 1.2755 1.3021 1.3298 1.3587 1.3889 1.4205 1.4535 1.4881 1.5244 1.5625 1.6026 1.6447 1.6892 1.7361 1.7857 1.8382 1.8939 TC0R TC0OUT (KHz) 1.9531 2.0161 2.0833 2.1552 2.2321 2.3148 2.4038 2.5000 2.6042 2.7174 2.8409 2.9762 3.1250 3.2895 3.4722 3.6765 3.9063 4.1667 4.4643 4.8077 5.2083 5.6818 6.2500 6.9444 7.8125 8.9286 10.4167 12.5000 15.6250 20.8333 31.2500 62.5000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255
Table 8-2. TC0OUT Frequency Table for Fosc = 4MHz, TC0 Rate = Fcpu/8
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Fosc = 16MHz, TC0 Rate = Fcpu/8
TC0R TC0OUT (KHz) 0.9766 0.9804 0.9843 0.9881 0.9921 0.9960 1.0000 1.0040 1.0081 1.0121 1.0163 1.0204 1.0246 1.0288 1.0331 1.0373 1.0417 1.0460 1.0504 1.0549 1.0593 1.0638 1.0684 1.0730 1.0776 1.0823 1.0870 1.0917 1.0965 1.1013 1.1062 1.1111 1.1161 1.1211 1.1261 1.1312 1.1364 1.1416 1.1468 1.1521 1.1574 1.1628 1.1682 1.1737 1.1792 1.1848 1.1905 1.1962 1.2019 1.2077 1.2136 1.2195 1.2255 1.2315 1.2376 1.2438 TC0R TC0OUT (KHz) 1.2500 1.2563 1.2626 1.2690 1.2755 1.2821 1.2887 1.2953 1.3021 1.3089 1.3158 1.3228 1.3298 1.3369 1.3441 1.3514 1.3587 1.3661 1.3736 1.3812 1.3889 1.3966 1.4045 1.4124 1.4205 1.4286 1.4368 1.4451 1.4535 1.4620 1.4706 1.4793 1.4881 1.4970 1.5060 1.5152 1.5244 1.5337 1.5432 1.5528 1.5625 1.5723 1.5823 1.5924 1.6026 1.6129 1.6234 1.6340 1.6447 1.6556 1.6667 1.6779 1.6892 1.7007 1.7123 1.7241 TC0R TC0OUT (KHz) 1.7361 1.7483 1.7606 1.7730 1.7857 1.7986 1.8116 1.8248 1.8382 1.8519 1.8657 1.8797 1.8939 1.9084 1.9231 1.9380 1.9531 1.9685 1.9841 2.0000 2.0161 2.0325 2.0492 2.0661 2.0833 2.1008 2.1186 2.1368 2.1552 2.1739 2.1930 2.2124 2.2321 2.2523 2.2727 2.2936 2.3148 2.3364 2.3585 2.3810 2.4038 2.4272 2.4510 2.4752 2.5000 2.5253 2.5510 2.5773 2.6042 2.6316 2.6596 2.6882 2.7174 2.7473 2.7778 2.8090 TC0R TC0OUT (KHz) 2.8409 2.8736 2.9070 2.9412 2.9762 3.0120 3.0488 3.0864 3.1250 3.1646 3.2051 3.2468 3.2895 3.3333 3.3784 3.4247 3.4722 3.5211 3.5714 3.6232 3.6765 3.7313 3.7879 3.8462 3.9063 3.9683 4.0323 4.0984 4.1667 4.2373 4.3103 4.3860 4.4643 4.5455 4.6296 4.7170 4.8077 4.9020 5.0000 5.1020 5.2083 5.3191 5.4348 5.5556 5.6818 5.8140 5.9524 6.0976 6.2500 6.4103 6.5789 6.7568 6.9444 7.1429 7.3529 7.5758 TC0R TC0OUT (KHz) 7.8125 8.0645 8.3333 8.6207 8.9286 9.2593 9.6154 10.0000 10.4167 10.8696 11.3636 11.9048 12.5000 13.1579 13.8889 14.7059 15.6250 16.6667 17.8571 19.2308 20.8333 22.7273 25.0000 27.7778 31.2500 35.7143 41.6667 50.0000 62.5000 83.3333 125.0000 250.0000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255
Table 8-3. TC0OUT Frequency Table for Fosc = 16MHz, TC0 Rate = Fcpu/8
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TIMER COUNTER 1 (TC1)
OVERVIEW
The timer counter 1 (TC1) is used to generate an interrupt request when a specified time interval has elapsed. TC1 has a auto re-loadable counter that consists of two parts: an 8-bit reload register (TC1R) into which you write the
Aload1 TC1R reload data buffer Internal P5.3 I/O circuit
Buzzer
TC1out
Auto. reload
O 2
P5.3
R Compare
PWM PWM1OUT
TC1enb load
S
fcpu
/2(8-TC1Rate)
CPUM0
TC1C 8-bit binary counter
TC1 Time out
counter reference value, and an 8-bit counter register (TC1C) whose value is automatically incremented by counter logic. Figure 8-6. Timer Count TC1 Block Diagram The main purposes of the TC1 timer is as following.
8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock frequency. Arbitrary frequency output (Buzzer output): Outputs selectable clock frequencies to the BZ1 pin (P5.3). PWM function: PWM output can be generated by the PWM1OUT bit and output to PWM1OUT pin (P5.3).
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TC1M MODE REGISTER
The TC1M is an 8-bit read/write timer mode register. By loading different value into the TC1M register, users can modify the timer clock frequency dynamically as program executing. Eight rates for TC1 timer can be selected by TC1RATE0 ~ TC1RATE2 bits. The range is from fcpu/2 to fcpu/256. The TC1M initial value is zero and the rate is fcpu/256. The bit7 of TC1M called TC1ENB is the control bit to start TC1 timer. The combination of these bits is to determine the TC1 timer clock frequency and the intervals.
TC1M initial value = 0000 0000
0DCH TC1M
Bit 7 TC1ENB R/W
Bit 6 Bit 5 Bit 4 TC1RATE2 TC1RATE1 TC1RATE0 R/W R/W R/W
Bit 3 TC1CKS R/W
Bit 2 ALOAD1 R/W
Bit 1 TC1OUT R/W
Bit 0 PWM1OUT R/W
TC1ENB: TC1 counter/BZ1/PWM1OUT enable bit. 0 = disable, 1 = enable. TC1RATE2~TC1RATE0: TC1 internal clock select bits. 000 = fcpu/256, 001 = fcpu/128, ... , 110 = fcpu/4, 111 = fcpu/2. TC1CKS: TC1 clock source select bit. "0" = Fcpu, "1" = External clock come from INT1/P0.1 pin. TC1 will be an event counter.. ALOAD1: TC1 auto-reload function control bit. 0 = none auto-reload, 1 = auto-reload. TC1OUT: TC1 time-out toggle signal output control bit. 0 = To disable TC1 signal output and to enable P5.3's I/O function, 1 = To enable TC1's signal output and to disable P5.3's I/O function. (Auto-disable the PWM1OUT function.) PWM1OUT: TC1's PWM output control bit. 0 = To disable the PWM output, 1 = To enable the PWM output (The TC1OUT control bit must = 0 )
Note1: When TC1CKS=1, TC0 became an external event counter. No more P0.1 interrupt request will be raised. (P0.1IRQ will be always 0) Note2: The ICE S8KC do not support the PWM0OUT and TC0OUT Function. The PWM0OUT and TC0OUT must use the S8KD ICE (or later) to verify the function.
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TC1C COUNTING REGISTER
TC1C is an 8-bit counter register for the timer counter (TC1). TC1C must be reset whenever the TC1ENB is set "1" to start the timer. TC0C is incremented by one with a clock pulse which the frequency is determined by TC0RATE0 ~ TC0RATE2. When TC0C has incremented to "0FFH", it is will be cleared to "00H" in next clock and an overflow is generated. Under TC1 interrupt service request (TC1IEN) enable condition, the TC1 interrupt request flag will be set "1" and the system executes the interrupt service routine.
TC1C initial value = xxxx xxxx
0DDH TC1C
Bit 7 TC1C7 R/W
Bit 6 TC1C6 R/W
Bit 5 TC1C5 R/W
Bit 4 TC1C4 R/W
Bit 3 TC1C3 R/W
Bit 2 TC1C2 R/W
Bit 1 TC1C1 R/W
Bit 0 TC1C0 R/W
The interval time of TC1 basic timer table.
TC1RATE TC1CLOCK 000 001 010 011 100 101 110 111 fcpu/256 fcpu/128 fcpu/64 fcpu/32 fcpu/16 fcpu/8 fcpu/4 fcpu/2
High speed mode (fcpu = 3.58MHz / 4) Max overflow interval One step = max/256 73.2 ms 286us 36.6 ms 143us 18.3 ms 71.5us 9.15 ms 35.8us 4.57 ms 17.9us 2.28 ms 8.94us 1.14 ms 4.47us 0.57 ms 2.23us
Low speed mode (fcpu = 32768Hz / 4) Max overflow interval One step = max/256 8000 ms 31.25 ms 4000 ms 15.63 ms 2000 ms 7.8 ms 1000 ms 3.9 ms 500 ms 1.95 ms 250 ms 0.98 ms 125 ms 0.49 ms 62.5 ms 0.24 ms
Table 8-4. The Timing Table of Timer Count TC1
The equation of TC1C initial value is as following.
TC1C initial value = 256 - (TC1 interrupt interval time * input clock)
Example: To set 10ms interval time for TC1 interrupt at 3.58MHz high-speed mode. TC1C value (74H) = 256 - (10ms * fcpu/64) TC1C initial value = 256 - (TC1 interrupt interval time * input clock) = 256 - (10ms * 3.58 * 106 / 4 / 64) = 256 - (10-2 * 3.58 * 106 / 4 / 64) = 116 = 74H
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TC1R AUTO-LOAD REGISTER
TC1R is an 8-bit register for the TC1 auto-reload function. TC1R's value applies to TC1OUT and PWM1OUT functions. Under TC1OUT application, users must enable and set the TC1R register. The main purpose of TC1R is as following. Store the auto-reload value and set into TC1C when the TC1C overflow. (ALOAD1 = 1). Store the duty value of PWM1OUT function.
TC1R initial value = xxxx xxxx
0DEH TC1R
Bit 7 TC1R7 W
Bit 6 TC1R6 W
Bit 5 TC1R5 W
Bit 4 TC1R4 W
Bit 3 TC1R3 W
Bit 2 TC1R2 W
Bit 1 TC1R1 W
Bit 0 TC1R0 W
The equation of TC1R initial value is like TC1C as following.
TC1R initial value = 256 - (TC1 interrupt interval time * input clock)
Note: The TC1R is write-only register can't be process by INCMS, DECMS instructions.
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TC1 TIMER COUNTER OPERATION SEQUENCE
The TC1 timer's sequence of operation can be following. Set the TC1C initial value to setup the interval time. Set the TC1ENB to be "1" to enable TC1 timer counter. TC1C is incremented by one with each clock pulse which frequency is corresponding to TC1M selection. TC1C overflow if TC1C from FFH to 00H. When TC1C overflow occur, the TC1IRQ flag is set to be "1" by hardware. Execute the interrupt service routine. Users reset the TC1C value and resume the TC1 timer operation.
Example: Setup the TC1M and TC1C without auto-reload function.
B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET
FTC1IEN FTC1ENB A,#20H TC1M,A A,#74H TC1C,A FTC1IEN FTC1IRQ FTC1ENB
; To disable TC1 interrupt service ; To disable TC1 timer ; ; To set TC1 clock = fcpu / 64 ; To set TC1C initial value = 74H ;(To set TC1 interval = 10 ms) ; To enable TC1 interrupt service ; To clear TC1 interrupt request ; To enable TC1 timer
Example: Setup the TC1M and TC1C with auto-reload function.
B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0MOV B0BSET B0BCLR B0BSET B0BSET
FTC1IEN FTC1ENB A,#20H TC1M,A A,#74H TC1C,A TC1R,A FTC1IEN FTC1IRQ FTC1ENB ALOAD1
; To disable TC1 interrupt service ; To disable TC1 timer ; ; To set TC1 clock = fcpu / 64 ; To set TC1C initial value = 74H ; (To set TC1 interval = 10 ms) ; To set TC1R auto-reload register ; To enable TC1 interrupt service ; To clear TC1 interrupt request ; To enable TC1 timer ; To enable TC1 auto-reload function.
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Example: TC1 interrupt service routine without auto-reload function.
ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR MOV B0MOV . . JMP . . EXIT_INT: POP B0XCH RETI
8 INT_SERVICE
; Interrupt vector
A, ACCBUF
; B0XCH doesn't change C, Z flag ; Push ; Check TC1IRQ ; TC1IRQ = 0, exit interrupt vector ; Reset TC1IRQ ; Reload TC1C ; TC1 interrupt service routine ; End of TC1 interrupt service routine and exit interrupt vector
FTC1IRQ EXIT_INT FTC1IRQ A,#74H TC1C,A . . EXIT_INT . .
A, ACCBUF
; Pop ; Restore ACC value. ; Exit interrupt vector
Example: TC1 interrupt service routine with auto-reload.
ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR . . JMP . . EXIT_INT: POP B0XCH RETI
8 INT_SERVICE
; Interrupt vector
A, ACCBUF
; B0XCH doesn't change C, Z flag ; Push ; Check TC1IRQ ; TC1IRQ = 0, exit interrupt vector ; Reset TC1IRQ ; TC1 interrupt service routine ; End of TC1 interrupt service routine and exit interrupt vector
FTC1IRQ EXIT_INT FTC1IRQ . . EXIT_INT . .
A, ACCBUF
; Pop ; Restore ACC value. ; Exit interrupt vector
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TC1 CLOCK FREQUENCY OUTPUT (BUZZER)
TC1 timer counter provides a frequency output function. By setting the TC1 clock frequency, the clock signal is output to P5.3 and the P5.3 general purpose I/O function is auto-disable. The TC1 output signal divides by 2. The TC1 clock has many combinations and easily to make difference frequency. This function applies as buzzer output to output multi-frequency.
Figure 8-7. The TC1OUT Pulse Frequency Example: Setup TC1OUT output from TC1 to TC1OUT (P5.3). The external high-speed clock is 4MHz. The TC1OUT frequency is 1KHz. Because the TC1OUT signal is divided by 2, set the TC1 clock to 2KHz. The TC1 clock source is from external oscillator clock. TC1 rate is Fcpu/4. The TC1RATE2~TC1RATE1 = 110. TC1C = TC1R = 131.
MOV B0MOV MOV B0MOV B0MOV B0BSET B0BSET B0BSET
A,#01100000B TC1M,A A,#131 TC1C,A TC1R,A FTC1OUT FALOAD1 FTC1ENB
; Set the TC1 rate to Fcpu/4 ; Set the auto-reload reference value
; Enable TC1 output to P5.3 and disable P5.3 I/O function ; Enable TC1 auto-reload function ; Enable TC1 timer
Note: The TC1OUT frequency table is as TC0OUT frequency table. Please consult TC0OUT frequency table. (Table 7-2~7-5)
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PWM FUNCTION DESCRIPTION
OVERVIEW
PWM function is generated by TC0/TC1 timer counter and output the PWM signal to PWM0OUT pin (P5.4)/ PWM1OUT pin (P5.3). The 8-bit counter counts modulus 256, from 0-255, inclusive. The value of the 8-bit counter is compared to the contents of the reference register (TC0R/TC1R). When the reference register value (TC0R/TC1R) is equal to the counter value (TC0C/TC1C), the PWM output goes low. When the counter reaches zero, the PWM output is forced high. The low-to-high ratio (duty) of the PWM0/PWM1 output is TC0R/256 and TC1R/256. All PWM outputs remain inactive during the first 256 input clock signals. Then, when the counter value (TC0C/TC1C) changes from FFH back to 00H, the PWM output is forced to high level. The pulse width ratio (duty cycle) is defined by the contents of the reference register (TC0R/TC1R) and is programmed in increments of 1:256. The 8-bit PWM data register TC0R/TC1R is write only register. PWM output can be held at low level by continuously loading the reference register with 00H. Under PWM operating, to change the PWM's duty cycle is to modify the TC0R/TC1R.
Reference Register Value (TC0R/TC1R) 0000 0000 0000 0001 0000 0010 . . 1000 0000 1000 0001 . . 1111 1110 1111 1111
Duty
0/256 1/256 2/256 . . 128/256 129/256 . . 254/256 255/256
Table 8-5. The PWM Duty Cycle Table
0 TC0/TC1 Clock
1
..... 128
..... 254 255
0
1
..... 128
..... 254 255
TC0R/TC1R = 00H
High
Low
TC0R/TC1R = 01H
High
Low
TC0R/TC1R = 80H
High
Low
TC0R/TC1R = FFH
Low
Figure 8-8 The Output of PWM with different TC0R/TC1R.
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PWM PROGRAM DESCRIPTION
Example: Setup PWM0 output from TC0 to PWM0OUT (P5.4). The external high-speed oscillator clock is 4MHz. The duty of PWM is 30/256. The PWM frequency is about 1KHz. The PWM clock source is from external oscillator clock. TC0 rate is Fcpu/4. The TC0RATE2~TC0RATE1 = 110. TC0C = TC0R = 30.
MOV B0MOV MOV B0MOV MOV B0MOV B0BCLR B0BSET B0BSET
A,#01100000B TC0M,A A,#0x00 TC0C,A A,#30 TC0R,A FTC0OUT FPWM0OUT FTC0ENB
; Set the TC0 rate to Fcpu/4 ;First Time Initial TC0
; Set the PWM duty to 30/256
; Disable TC0OUT function. ; Enable PWM0 output to P5.4 and disable P5.4 I/O function ; Enable TC0 timer
Note1: The TC0R and TC1R are write-only registers. Don't process them using INCMS, DECMS instructions. Note2: Set TC0C at initial is to make first duty-cycle correct. After TC0 is enabled, don't modify TC0R value to avoid duty cycle error of PWM output. Example: Modify TC0R/TC1R registers' value.
MOV B0MOV INCMS B0MOV B0MOV
A, #30H TC0R, A BUF0 A, BUF0 TC0R, A
; Input a number using B0MOV instruction.
; Get the new TC0R value from the BUF0 buffer defined by ; programming.
Note2: That is better to set the TC0C and TC0R value together when PWM0 duty modified. It protects the PWM0 signal no glitch as PWM0 duty changing. That is better to set the TC1C and TC1R value together when PWM1 duty modified. It protects the PWM1 signal no glitch as PWM1 duty changing. Note3: The TC0OUT function must be set "0" when PWM0 output enable. The TC1OUT function must be set "0" when PWM1 output enable. Note4: The PWM can work with interrupt request.
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9
INTERRUPT
1
OVERVIEW
The SN8P1800 provides 7 interrupt sources, including four internal interrupts (T0, TC0, TC1 & SIO) and three external interrupts (INT0 ~ INT2). These external interrupts can wakeup the chip from power down mode to high-speed normal mode. The external clock input pins of INT0/INT1/INT2 are shared with P0.0/P0.1/P0.2 pins. Once interrupt service is executed, the GIE bit in STKP register will clear to "0" for stopping other interrupt request. When interrupt service exits, the GIE bit will set to "1" to accept the next interrupts' request. All of the interrupt request signals are stored in INTRQ register. The user can program the chip to check INTRQ's content for setting executive priority.
The interrupt trigger edge : INT0 ~ INT2 = falling edge
INTEN Interrupt enable register
T0 time out
T0IRQ
TC0 time out TC1 time out
TC0IRQ Interrupt vector address (0008H) INTRQ 7-bit Latchs TC1IRQ Interrupt enable gating Global interrupt request signal
SIO time out
SIOIRQ
INT0 trigger
P00IRQ
INT1 trigger INT2 trigger
P01IRQ
P02IRQ
Figure 9-1. The 7 Interrupts of SN8P1800 Note:The GIE bit must enable and all interrupt operations work.
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INTEN INTERRUPT ENABLE REGISTER
INTEN is the interrupt request control register including four internal interrupts, three external interrupts and SIO interrupt enable control bits. One of the register to be set "1" is to enable the interrupt request function. Once of the interrupt occur, the program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service routine when the returning interrupt service routine instruction (RETI) is executed.
INTEN initial value = x000 0000 0C9H Bit 7 Bit 6 0 TC1IEN INTEN R/W
Bit 5 TC0IEN R/W
Bit 4 T0IEN R/W
Bit 3 SIOIEN R/W
Bit 2 P02IEN R/W
Bit 1 P01IEN R/W
Bit 0 P00IEN R/W
P00IEN : External P0.0 interrupt control bit. 0 = disable, 1 = enable. P01IEN : External P0.1 interrupt control bit. 0 = disable, 1 = enable. P02IEN : External P0.2 interrupt control bit. 0 = disable, 1 = enable. SIOIEN : SIO interrupt control bit. 0 = disable, 1 = enable. T0IEN : T0 timer interrupt control bit. 0 = disable, 1 = enable. TC0IEN : Timer 0 interrupt control bit. 0 = disable, 1 = enable. TC1IEN : Timer 1 interrupt control bit. 0 = disable, 1 = enable.
INTRQ INTERRUPT REQUEST REGISTER
INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of these interrupt request occurs, the bit of the INTRQ register would be set "1". The INTRQ value needs to be clear by programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests occurring by the register and do the routine corresponding of the interrupt request.
INTRQ initial value = x000 0000
0C8H INTRQ
Bit 7 0 -
Bit 6 TC1IRQ R/W
Bit 5 TC0IRQ R/W
Bit 4 T0IRQ R/W
Bit 3 SIOIRQ R/W
Bit 2 P02IRQ R/W
Bit 1 P01IRQ R/W
Bit 0 P00IRQ R/W
P00IRQ : External P0.0 interrupt request bit. 0 = non-request, 1 = request. P01IRQ : External P0.1 interrupt request bit. 0 = non-request, 1 = request. P02IRQ : External P0.2 interrupt request bit. 0 = non-request, 1 = request. SIOIRQ : SIO interrupt request bit. 0 = non-request, 1 = request. T0IRQ : T0 timer interrupt request control bit. 0 = non request, 1 = request. TC0IRQ : TC0 timer interrupt request controls bit. 0 = non request, 1 = request. TC1IRQ : TC1 timer interrupt request controls bit. 0 = non request, 1 = request.
When interrupt occurs, the related request bit of INTRQ register will be set to "1" no matter the related enable bit of INTEN register is enabled or disabled. If the related bit of INTEN = 1 and the related bit of INTRQ is also set to be "1". As the result, the system will execute the interrupt vector (ORG 8). If the related bit of INTEN = 0, moreover, the system won't execute interrupt vector even when the related bit of INTRQ is set to be "1". Users need to be cautious with the operation under multi-interrupt situation.
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INTERRUPT OPERATION DESCRIPTION
SN8P1800 provides 7 interrupts. The operation of the 7 interrupts is as following.
GIE GLOBAL INTERRUPT OPERATION
GIE is the global interrupt control bit. All interrupts start work after the GIE = 1. It is necessary for interrupt service request. One of the interrupt requests occurs, and the program counter (PC) points to the interrupt vector (ORG 8) and the stack add 1 level.
STKP initial value = 0xxx 1111
0DFH STKP
Bit 7 GIE R/W
Bit 6 -
Bit 5 -
Bit 4 -
Bit 3 STKPB3 R/W
Bit 2 STKPB2 R/W
Bit 1 STKPB1 R/W
Bit 0 STKPB0 R/W
GIE: Global interrupt control bit. 0 = disable, 1 = enable.
Example: Set global interrupt control bit (GIE).
B0BSET
FGIE
; Enable GIE
Note: The GIE bit must enable and all interrupt operations work.
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INT0 (P0.0) INTERRUPT OPERATION
The INT0 is triggered by falling edge. When the INT0 trigger occurs, the P00IRQ will be set to "1" however the P00IEN is enable or disable. If the P00IEN = 1, the trigger event will make the P00IRQ to be "1" and the system enter interrupt vector. If the P00IEN = 0, the trigger event will make the P00IRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation.
Example: INT0 interrupt request setup.
B0BSET B0BCLR B0BSET
FP00IEN FP00IRQ FGIE
; Enable INT0 interrupt service ; Clear INT0 interrupt request flag ; Enable GIE
Example: INT0 interrupt service routine.
ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR . . EXIT_INT: POP B0XCH RETI
8 INT_SERVICE
; Interrupt vector
A, ACCBUF
; Store ACC value. ; Push ; Check P00IRQ ; P00IRQ = 0, exit interrupt vector ; Reset P00IRQ ; INT0 interrupt service routine
FP00IRQ EXIT_INT FP00IRQ . .
A, ACCBUF
; Pop ; Restore ACC value. ; Exit interrupt vector
Note: The PUSH and POP instruction only save L,H,R,Z,Y,X,PFLAG and RBANK registers but A register. User must save register A by B0XCH instruction when PUSH command is used.
INT1 (P0.1) INTERRUPT OPERATION
The INT1 is triggered by falling edge. When the INT1 trigger occurs, the P01IRQ will be set to "1" however the P01IEN is enable or disable. If the P01IEN = 1, the trigger event will make the P01IRQ to be "1" and the system enter interrupt vector. If the P01IEN = 0, the trigger event will make the P01IRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation.
Example: INT1 interrupt request setup.
B0BSET B0BCLR B0BSET
FP01IEN FP01IRQ FGIE
; Enable INT1 interrupt service ; Clear INT1 interrupt request flag ; Enable GIE
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Example: INT1 interrupt service routine.
ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR . . EXIT_INT: POP B0XCH RETI
8 INT_SERVICE
; Interrupt vector
A, ACCBUF
; Store ACC value. ; Push ; Check P01IRQ ; P01IRQ = 0, exit interrupt vector ; Reset P01IRQ ; INT1 interrupt service routine
FP01IRQ EXIT_INT FP01IRQ . .
A, ACCBUF
; Pop ; Restore ACC value. ; Exit interrupt vector
INT2 (P0.2) INTERRUPT OPERATION
The INT2 is triggered by falling edge. When the INT2 trigger occurs, the P02IRQ will be set to "1" however the P02IEN is enable or disable. If the P02IEN = 1, the trigger event will make the P02IRQ to be "1" and the system enter interrupt vector. If the P02IEN = 0, the trigger event will make the P02IRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation.
Example: INT2 interrupt request setup.
B0BSET B0BCLR B0BSET
FP02IEN FP02IRQ FGIE
; Enable INT2 interrupt service ; Clear INT2 interrupt request flag ; Enable GIE
Example: INT2 interrupt service routine.
ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR . . EXIT_INT: POP B0XCH RETI
8 INT_SERVICE
; Interrupt vector
A, ACCBUF
; Store ACC value. ; Push ; Check P02IRQ ; P02IRQ = 0, exit interrupt vector ; Reset P02IRQ ; INT2 interrupt service routine
FP02IRQ EXIT_INT FP02IRQ . .
A, ACCBUF
; Pop ; Restore ACC value. ; Exit interrupt vector
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T0 INTERRUPT OPERATION
When the T0C counter occurs overflow, the T0IRQ will be set to "1" however the T0IEN is enable or disable. If the T0IEN = 1, the trigger event will make the T0IRQ to be "1" and the system enter interrupt vector. If the T0IEN = 0, the trigger event will make the T0IRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation.
Example: T0 interrupt request setup.
B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET B0BSET
FT0IEN FT0ENB A, #20H T0M, A A, #74H T0C, A FT0IEN FT0IRQ FT0ENB FGIE
; Disable T0 interrupt service ; Disable T0 timer ; ; Set T0 clock = Fcpu / 64 ; Set T0C initial value = 74H ; Set T0 interval = 10 ms ; Enable T0 interrupt service ; Clear T0 interrupt request flag ; Enable T0 timer ; Enable GIE
Example: T0 interrupt service routine.
ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR MOV B0MOV . . EXIT_INT: POP B0XCH RETI
8 INT_SERVICE
; Interrupt vector
A, ACCBUF
; Store ACC value. ; Push ; Check T0IRQ ; T0IRQ = 0, exit interrupt vector ; Reset T0IRQ ; Reset T0C. ; T0 interrupt service routine
FT0IRQ EXIT_INT FT0IRQ A, #74H T0C, A . .
A, ACCBUF
; Pop ; Restore ACC value. ; Exit interrupt vector
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TC0 INTERRUPT OPERATION
When the TC0C counter occurs overflow, the TC0IRQ will be set to "1" however the TC0IEN is enable or disable. If the TC0IEN = 1, the trigger event will make the TC0IRQ to be "1" and the system enter interrupt vector. If the TC0IEN = 0, the trigger event will make the TC0IRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation.
Example: TC0 interrupt request setup.
B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET B0BSET
FTC0IEN FTC0ENB A, #20H TC0M, A A, #74H TC0C, A FTC0IEN FTC0IRQ FTC0ENB FGIE
; Disable TC0 interrupt service ; Disable TC0 timer ; ; Set TC0 clock = Fcpu / 64 ; Set TC0C initial value = 74H ; Set TC0 interval = 10 ms ; Enable TC0 interrupt service ; Clear TC0 interrupt request flag ; Enable TC0 timer ; Enable GIE
Example: TC0 interrupt service routine.
ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR MOV B0MOV . . EXIT_INT: POP B0XCH RETI
8 INT_SERVICE
; Interrupt vector
A, ACCBUF
; Store ACC value. ; Push ; Check TC0IRQ ; TC0IRQ = 0, exit interrupt vector ; Reset TC0IRQ ; Reset TC0C. ; TC0 interrupt service routine
FTC0IRQ EXIT_INT FTC0IRQ A, #74H TC0C, A . .
A, ACCBUF
; Pop ; Restore ACC value. ; Exit interrupt vector
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TC1 INTERRUPT OPERATION
When the TC1C counter occurs overflow, the TC1IRQ will be set to "1" however the TC1IEN is enable or disable. If the TC1IEN = 1, the trigger event will make the TC1IRQ to be "1" and the system enter interrupt vector. If the TC1IEN = 0, the trigger event will make the TC1IRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation.
Example: TC1 interrupt request setup.
B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET B0BSET
FTC1IEN FT C1ENB A, #20H TC1M, A A, #74H TC1C, A FTC1IEN FTC1IRQ FTC1ENB FGIE
; Disable TC1 interrupt service ; Disable TC1 timer ; ; Set TC1 clock = Fcpu / 64 ; Set TC1C initial value = 74H ; Set TC1 interval = 10 ms ; Enable TC1 interrupt service ; Clear TC1 interrupt request flag ; Enable TC1 timer ; Enable GIE
Example: TC1 interrupt service routine.
ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR MOV B0MOV . . EXIT_INT: POP B0XCH RETI
8 INT_SERVICE
; Interrupt vector
A, ACCBUF
; Store ACC value. ; Push ; Check TC1IRQ ; TC1IRQ = 0, exit interrupt vector ; Reset TC1IRQ ; Reset TC1C. ; TC1 interrupt service routine
FTC1IRQ EXIT_INT FTC1IRQ A, #74H TC1C, A . .
A, ACCBUF
; Pop ; Restore ACC value. ; Exit interrupt vector
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SIO INTERRUPT OPERATION
When the SIO finished transmitting, the SIOIRQ will be set to "1" however the SIOIEN is enable or disable. If the SIOIEN = 1, the trigger event will make the SIOIRQ to be "1" and the system enter interrupt vector. If the SIOIEN = 0, the trigger event will make the SIOIRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation.
Example: SIO interrupt request setup.
B0BSET B0BCLR B0BSET
FSIOIEN FSIOIRQ FGIE
; Enable SIO interrupt service ; Clear SIO interrupt request flag ; Enable GIE
Example: SIO interrupt service routine.
ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR . . EXIT_INT: POP B0XCH RETI
8 INT_SERVICE
; Interrupt vector
A, ACCBUF
; Store ACC value. ; Push ; Check SIOIRQ ; SIOIRQ = 0, exit interrupt vector ; Reset SIOIRQ ; SIO interrupt service routine
FSIOIRQ EXIT_INT FSIOIRQ . .
A, ACCBUF
; Pop ; Restore ACC value. ; Exit interrupt vector
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MULTI-INTERRUPT OPERATION
In most conditions, the software designer uses more than one interrupt request. Processing multi-interrupt request needs to set the priority of these interrupt requests. The IRQ flags of the 7 interrupt are controlled by the interrupt event occurring. But the IRQ flag set doesn't mean the system to execute the interrupt vector. The IRQ flags can be triggered by the events without interrupt enable. Just only any the event occurs and the IRQ will be logic "1". The IRQ and its trigger event relationship is as the below table.
Interrupt Name P00IRQ P01IRQ P02IRQ T0IRQ TC0IRQ TC1IRQ SIOIRQ
Trigger Event Description P0.0 trigger. Falling edge. P0.1 trigger. Falling edge. P0.2 trigger. Falling edge. T0C overflow. TC0C overflow. TC1C overflow. End of SIO transmitter operating.
There are two things need to do for multi-interrupt. One is to make a good priority for these interrupt requests. Two is using IEN and IRQ flags to decide executing interrupt service routine or not. Users have to check interrupt control bit and interrupt request flag in interrupt vector. There is a simple routine as following.
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Example: How does users check the interrupt request in multi-interrupt situation?
ORG B0XCH PUSH INTP00CHK: B0BTS1 JMP B0BTS0 JMP INTP01CHK: B0BTS1 JMP B0BTS0 JMP INTP02CHK: B0BTS1 JMP B0BTS0 JMP INTT0CHK: B0BTS1 JMP B0BTS0 JMP INTTC0CHK: B0BTS1 JMP B0BTS0 JMP INTTC1HK: B0BTS1 JMP B0BTS0 JMP INTSIOCHK: B0BTS1 JMP B0BTS0 JMP INT_EXIT: POP B0XCH RETI
8 A, ACCBUF
; Interrupt vector ; Store ACC value. ; Push ; Check INT0 interrupt request ; Check P00IEN ; Jump check to next interrupt ; Check P00IRQ ; Jump to INT0 interrupt service routine ; Check INT1 interrupt request ; Check P01IEN ; Jump check to next interrupt ; Check P01IRQ ; Jump to INT1 interrupt service routine ; Check INT2 interrupt request ; Check P02IEN ; Jump check to next interrupt ; Check P02IRQ ; Jump to INT2 interrupt service routine ; Check T0 interrupt request ; Check T0IEN ; Jump check to next interrupt ; Check T0IRQ ; Jump to T0 interrupt service routine ; Check TC0 interrupt request ; Check TC0IEN ; Jump check to next interrupt ; Check TC0IRQ ; Jump to TC0 interrupt service routine ; Check TC1 interrupt request ; Check TC1IEN ; Jump check to next interrupt ; Check TC1IRQ ; Jump to TC1 interrupt service routine ; Check SIO interrupt request ; Check SIOIEN ; Jump to exit of IRQ ; Check SIOIRQ ; Jump to SIO interrupt service routine ; Pop ; Restore ACC value. ; Exit interrupt vector
FP00IEN INTP01CHK FP00IRQ INTP00 FP01IEN INTP02CHK FP01IRQ INTP01 FP02IEN INTT0CHK FP02IRQ INTP02 FT0IEN INTTC0CHK FT0IRQ INTT0 FTC0IEN INTTC1CHK FTC0IRQ INTTC0 FTC1IEN INTSIOCHK FTC1IRQ INTTC1 FSIOIEN INT_EXIT FSIOIRQ INTSIO
A, ACCBUF
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10 TRANSCEIVER (SIO) SERIAL INPUT/OUTPUT
OVERVIEW
The SN8P1800provides an 8-bit SIO interface circuit with clock rate selection. The SIOM register can control SIO operating function, such as: transmit/receive, clock rate, transfer edge and starting this circuit. This SIO circuit will TX or RX 8-bit data automatically by setting SENB and START bits in SIOM register. The SIOB is an 8-bit buffer, which is designed to store transfer data. SIOC and SIOR are designed to generate SIO's clock source with auto-reload function. The 3-bit I/O counter can monitor the operation of SIO and announce an interrupt request after transmitting/receiving 8 bits data. After transferring 8-bit data, this circuit will be disabled automatically and re-transfer data by programming SIOM register.
Senb SI/P5.1 pin Sckmd SCK/P5.0 pin CPUM1,0 SCK sources CPUM1,0 SIOC 8-bit binary counter Senb Srate Auto_reload SIOR register Senb
Data bus
SIOM register
Senb, TxRx SO/P5.2 pin
SIOB 8-bit buffer CPUM1,0
3-bit I/O counter Sckmd Sedge reset Senb
SIO Time out
Figure 10-1. SIO Interface Circuit Diagram
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Figure 9-2 shows a typical transfer between two micro-controllers. Process 1 sends SCK for initial the data transfer. Both processors must work in the same clock edge direction, then both controllers would send and receive data at the same time.
SDI
SDO
SIOM Register
SIOM Register
SIOB 8 Bit Buffer MSB LSB
SDO
SDI
SIOB 8 Bit Buffer MSB LSB
SIO Clock SCK PROCESS 1 SCK PROCESS 2
Figure 10-2. SIO Data Transfer Diagram
SIOM MODE REGISTER
SIOM initial value = 0000 x000
0B4H SIOM
Bit 7 SENB R/W
Bit 6 START R/W
Bit 5 SRATE1 R/W
Bit 4 SRATE0 R/W
Bit 3 0 -
Bit 2 SCKMD R/W
Bit 1 SEDGE R/W
Bit 0 TXRX R/W
SENB: SIO function control bit. 0 = disable (P5.0~P5.2 is general purpose port), 1 = enable (P5.0~P5.2 is SIO pins). START: SIO progress control bit. 0 = End of transfer, 1 = progressing. SRATE1, 0: SIO's transfer rate select bit. 00 = fcpu, 01 = fcpu/32, 10 = fcpu/16, 11 = fcpu/8. (Note: These 2-bits are workless when SCKMD=1) SCKMD: SIO's clock mode select bit. 0 = internal, 1 = external mode. SEDGE: SIO's transfer clock edge select bit. 0 = falling edge, 1 = raising edge. TXRX: SIO's transfer direction select bit. 0 = receiver only , 1 = transmitter/receiver full duplex.
Note 1: If SCKMD=1 for external clock, the SIO is in SLAVE mode. If SCKMD=0 for internal clock, the SIO is in MASTER mode. Note 2: Don't set SENB and START bits in the same time. That makes the SIO function error.
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Because SIO function is shared with Port5 for P5.0 as SCK, P5.1 as SI and P5.2 as SO The following table shown the Port5[2:0] I/O mode behavior and setting when SIO function enable and disable SENB=1 (SIO Function Enable) (SCKMD=1) P5.0/SCK SIO source = External clock (SCKMD=0) SIO source = Internal clock P5.1/SI P5.0 will change to Input mode automatically, no matter what P5M setting P5.0 will change to Output mode automatically, no matter what P5M setting
P5.1 must be set as Input mode in P5M ,or the SIO function will be abnormal (TXRX=1) P5.2 will change to Output mode automatically, no matter what P5M setting P5.2 will change to Input mode automatically, no matter what P5M setting
P5.2/SO
SIO = Transmitter/Receiver (TXRX=0) SIO = Receiver only
SENB=0 (SIO Function Disable) P5.0/P5.1/P5.2 Port5[2:0] I/O mode are fully controlled by P5M when SIO function Disable
SIOB DATA BUFFER
SIOB initial value = 0000 0000
0B6H SIOB
Bit 7 SIOB7 R/W
Bit 6 SIOB6 R/W
Bit 5 SIOB5 R/W
Bit 4 SIOB4 R/W
Bit 3 SIOB3 R/W
Bit 2 SIOB2 R/W
Bit 1 SIOB1 R/W
Bit 0 SIOB0 R/W
SIOB is the SIO data buffer register. It stores serial I/O transmit and receive data.
SIOR REGISTER DESCRIPTION
SIOR initial value = 0000 0000
0B5H SIOR
Bit 7 SIOR7 W
Bit 6 SIOR6 W
Bit 5 SIOR5 W
Bit 4 SIOR4 W
Bit 3 SIOR3 W
Bit 2 SIOR2 W
Bit 1 SIOR1 W
Bit 0 SIOR0 W
The SIOR is designed for the SIO counter to reload the counted value when end of counting. It is like a post-scaler of SIO clock source and let SIO has more flexible to setting SCK range. Users can set the SIOR value to setup SIO transfer time. To setup SIOR value equation to desire transfer time is as following.
SCK frequency = SIO rate / (256 - SIOR)
SIOR = 256 - ( 1 / ( SCK frequency ) * SIO rate / 2 )
Example: Setup the SIO clock to be 5KHz. Fosc = 3.58MHz. SIO's rate = Fcpu = Fosc/4. SIOR = 256 - (1/(5KHz) * 3.58MHz/4) = 256 - 89 = 167
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SIO MASTER OPERATING DESCRIPTION
Under master-transmitter situation, the SCK has two directions as following.
SCK
SCK
Figure 10-3. The Two SCK Directions of SIO Master Operation
RISING EDGE TRANSMITTER/RECEIVER MODE
Example: Master Tx/Rx rising edge
MOV B0MOV MOV B0MOV MOV B0MOV B0BSET CHK_END: B0BTS0 JMP B0MOV MOV
A,TXDATA SIOB,A A,#0FFH SIOR,A A,#10000011B SIOM,A FSTART FSTART CHK_END A,SIOB RXDATA,A
; Load transmitted data into SIOB register. ; Set SIO clock with auto-reload function. ; Setup SIOM and enable SIO function. Rising edge. ; Start transfer and receiving SIO data. ; Wait the end of SIO operation. ; Save SIOB data into RXDATA buffer.
TX/RX data
SCK
SI
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
SO
DO0
LSB
DO1
DO2
DO3
DO4
DO5
DO6
DO7
MSB
Figure 10-4. The Rising Edge Timing Diagram of Master Transfer and Receiving Operation
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FALLING EDGE TRANSMITTER/RECEIVER MODE
Example: Master Tx/Rx falling edge
MOV B0MOV MOV B0MOV MOV B0MOV B0BSET CHK_END: B0BTS0 JMP B0MOV MOV
A,TXDATA SIOB,A A,#0FFH SIOR,A A,#10000001B SIOM,A FSTART FSTART CHK_END A,SIOB RXDATA,A
; Load transmitted data into SIOB register. ; Set SIO clock with auto-reload function. ; Setup SIOM and enable SIO function. Falling edge. ; Start transfer and receiving SIO data. ; Wait the end of SIO operation. ; Save SIOB data into RXDATA buffer.
TX/RX data
SCK
SI
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
SO
DO0
LSB
DO1
DO2
DO3
DO4
DO5
DO6
DO7
MSB
Figure 10-5. The Falling Edge Timing Diagram of Master Transfer and Receiving Operation
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RISING EDGE RECEIVER MODE
Example: Master Rx rising edge
MOV B0MOV MOV B0MOV B0BSET CHK_END: B0BTS0 JMP B0MOV MOV
A,#0FFH SIOR,A A,#10000010B SIOM,A FSTART FSTART CHK_END A,SIOB RXDATA,A
; Set SIO clock with auto-reload function. ; Setup SIOM and enable SIO function. Rising edge. ; Start receiving SIO data. ; Wait the end of SIO operation. ; Save SIOB data into RXDATA buffer.
RX data
SCK
SI
DI0
LSB
DI1
DI2
DI3
DI4
DI5
DI6
DI7
MSB
SO
Normal I/O Application
Figure 10-6. The Rising Edge Timing Diagram of Master Receiving Operation
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FALLING EDGE RECEIVER MODE
Example: Master Rx falling edge
MOV B0MOV MOV B0MOV B0BSET CHK_END: B0BTS0 JMP B0MOV MOV
A,#0FFH SIOR,A A,#10000000B SIOM,A FSTART FSTART CHK_END A,SIOB RXDATA,A
; Set SIO clock with auto-reload function. ; Setup SIOM and enable SIO function. Falling edge. ; Start receiving SIO data. ; Wait the end of SIO operation. ; Save SIOB data into RXDATA buffer.
RX data
SCK
SI
DI0
LSB
DI1
DI2
DI3
DI4
DI5
DI6
DI7
MSB
SO
Normal I/O Application
Figure 10-7. The Falling Edge Timing Diagram of Master Receiving Operation
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SIO SLAVE OPERATING DESCRIPTION
Under slave-receiver situation, the SCK has four phases as following.
SCK1
SCK2
SCK3
SCK4
Figure 10-8. The Four Phases SCK clock of SIO Slave Operation.
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RISING EDGE TRANSMITTER/RECEIVER MODE
Example: Slave Tx/Rx rising edge
MOV B0MOV MOV B0MOV B0BSET CHK_END: B0BTS0 JMP B0MOV MOV
A,TXDATA SIOB,A A,# 10000111B SIOM,A FSTART FSTART CHK_END A,SIOB RXDATA,A
; Load transfer data into SIOB register. ; Setup SIOM and enable SIO function. Rising edge. ; Start transfer and receiving SIO data. ; Wait the end of SIO operation. ; Save SIOB data into RXDATA buffer.
TX/RX data
SCK1
SI
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
SO
DO0
LSB
TX/RX data
DO1
DO2
DO3
DO4
DO5
DO6
DO7
MSB
SCK2
SI
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
SO
DO0
LSB
DO1
DO2
DO3
DO4
DO5
DO6
DO7
MSB
Figure 10-9. The Rising Edge Timing Diagram of Slave Transfer and Receiving Operation
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FALLING EDGE TRANSMITTER/RECEIVER MODE
Example: Slave Tx/Rx falling edge
MOV B0MOV MOV B0MOV B0BSET CHK_END: B0BTS0 JMP B0MOV MOV
A,TXDATA SIOB,A A,# 10000101B SIOM,A FSTART FSTART CHK_END A,SIOB RXDATA,A
; Load transfer data into SIOB register. ; Setup SIOM and enable SIO function. Falling edge. ; Start transfer and receiving SIO data. ; Wait the end of SIO operation. ; Save SIOB data into RXDATA buffer.
TX/RX data
SCK3
SI
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
SO
DO0
LSB
TX/RX data
DO1
DO2
DO3
DO4
DO5
DO6
DO7
MSB
SCK4
SI
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
SO
DO0
LSB
DO1
DO2
DO3
DO4
DO5
DO6
DO7
MSB
Figure 10-10. The Falling Edge Timing Diagram of Slave Transfer and Receiving Operation
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RISING EDGE RECEIVER MODE
Example: Slave Rx rising edge
MOV B0MOV B0BSET CHK_END: B0BTS0 JMP B0MOV MOV
A,# 10000110B SIOM,A FSTART FSTART CHK_END A,SIOB RXDATA,A
; Setup SIOM and enable SIO function. Rising edge. ; Start receiving SIO data. ; Wait the end of SIO operation. ; Save SIOB data into RXDATA buffer.
RX data
SCK3
SI
DI0
LSB
DI1
DI2
DI3
DI4
DI5
DI6
DI7
MSB
SO
RX data
Normal I/O Application
SCK4
SI
DI0
LSB
DI1
DI2
DI3
DI4
DI5
DI6
DI7
MSB
SO
Normal I/O Application
Figure 10-11. The Rising Edge Timing Diagram of Slave Receiving Operation
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FALLING EDGE RECEIVER MODE
Example: Slave Rx falling edge
MOV B0MOV B0BSET CHK_END: B0BTS0 JMP B0MOV MOV
A,# 10000100B SIOM,A FSTART FSTART CHK_END A,SIOB RXDATA,A
; Setup SIOM and enable SIO function. Falling edge. ; Start receiving SIO data. ; Wait the end of SIO operation. ; Save SIOB data into RXDATA buffer.
RX data
SCK1
SI
DI0
LSB
DI1
DI2
DI3
DI4
DI5
DI6
DI7
MSB
SO
RX data
Normal I/O Application
SCK2
SI
DI0
LSB
DI1
DI2
DI3
DI4
DI5
DI6
DI7
MSB
SO
Normal I/O Application
Figure 10-12. The Falling Edge Timing Diagram of Slave Receiving Operation
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SIO INTERRUPT OPERATION DESCRIPTION
The SIO provides an interrupt function. Users can process SIO data after the SIO interrupt request occurring. There is a example for the application as following.
Example: SIO interrupt demo routine.
Main: MOV B0MOV B0BSET . . JMP A,# 10000100B SIOM,A FSTART . . MAIN ; Setup SIOM and enable SIO function. Falling edge. ; Start transfer SIO data.
ORG B0XCH PUSH B0BTS1 JMP B0MOV MOV B0BCLR INT_EXIT: POP B0XCH
8 A, ACCBUF
; Interrupt vector
FSIOIRQ INT_EXIT A,SIOB RXDATA,A FSIOIRQ
; Save SIOB data into RXDATA buffer. ; Clear SIO interrupt request flag.
A, ACCBUF
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11 I/O PORT
OVERVIEW
The SN8P1800 provides up to 5 ports for users' application, consisting of one input only port (P0), four I/O ports (P1, P2, P4, P5). The direction of I/O port is selected by PnM register.
Port1,Port4,Port5 structure Port0.0~P0.2 structure
PUR PnM, PnUR PUR PnM
Pin
P0UR
Pin
Int. bus PnM
Latch
Int. bus
PnM
Port6 structure
Port3 structure
PnM
PnM
PUR
Pin
Int. bus
P6HSEG, P6LSEG
Pin
PnM
Latch
Int. bus
LCD waveform
P3LCD
LCD waveform
PnM
Figure 11-1. The I/O Port Block Diagram
Note : All of the latch output circuits are push-pull structures.
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I/O PORT FUNCTION TABLE
Port/Pin I/O Function Description General-purpose input function External interrupt (INT0~INT2) Wakeup for power down mode General-purpose input function Wakeup for power down mode LCD common General-purpose input/output function Wakeup for power down mode General-purpose output function LCD segment General-purpose input function LCD segment General-purpose input/output function ADC analog signal input General-purpose input/output function SIO clock pin. General-purpose input/output function SIO data input pin. General-purpose input/output function SIO data output pin. General-purpose input/output function General-purpose input/output function LCD segment Table 11-1. I/O Function Table Remark Programmable pull-up
P0.0~P0.2
I
Programmable pull-up
P0.3~P0.5 P1.0~P1.5 P2.0~P2.7 P3.0~P3.7 P4.0~P4.7 P5.0 P5.1 P5.2 P5.3~P5.4 P6.0~P6.7
I I/O O I/O I/O I/O I/O I I/O O I/O I/O
Programmable pull-up
Pull-up at input mode Programmable pull-up Programmable pull-up
P5M.1 must be set "0" P5M.1 must be set "1"
Pull-up at input mode
PULL-UP RESISTOR (PnUR) REGISTER
PnUR initial value = 0000 0000 PnUR
Bit 7 Pn7R R/W
Bit 6 Pn6R R/W
Bit 5 Pn5R R/W
Bit 4 Pn4R R/W
Bit 3 Pn3R R/W
Bit 2 Pn2R R/W
Bit 1 Pn1R R/W
Bit 0 Pn0R R/W
PnUR : The n expressed 0, 1, 4, 5. Pn7R ~ Pn0R : Pull-up resistor control bit. 0 = without pull up resistor, 1 = with pull up resistor.
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I/O PORT MODE
The port direction is programmed by PnM register. Port 0 is always input mode. Port 1,2,4 and 5 can select input or output direction.
P1M initial value = xx00 0000
0C1H P1M
Bit 7 0 -
Bit 6 0 -
Bit 5 0 -
Bit 4 0 -
Bit 3 P13M R/W
Bit 2 P12M R/W
Bit 1 P11M R/W
Bit 0 P10M R/W
P10M~P13M: P1.0~P1.3 I/O direction control bit. 0 = input mode, 1 = output mode.
P4M initial value = 0000 0000
0C4H P4M
Bit 7 P47M R/W
Bit 6 P46M R/W
Bit 5 P45M R/W
Bit 4 P44M R/W
Bit 3 P43M R/W
Bit 2 P42M R/W
Bit 1 P41M R/W
Bit 0 P40M R/W
P40M~P47M: P4.0~P4.7 I/O direction control bit. 0 = input mode, 1 = output mode.
P5M initial value = 0000 0000
0C5H P5M
Bit 7 0 -
Bit 6 0 -
Bit 5 0 -
Bit 4 P54M R/W
Bit 3 P53M R/W
Bit 2 P52M R/W
Bit 1 P51M R/W
Bit 0 P50M R/W
P50M~P54M: P5.0~P5.4 I/O direction control bit. 0 = input mode, 1 = output mode. The each bit of PnM is set to "0", the I/O pin is input mode. The each bit of PnM is set to "1", the I/O pin is output mode.
The PnM registers are read/write bi-direction registers. Users can program them by bit control instructions (B0BSET, B0BCLR).
Example: I/O mode selecting.
CLR CLR CLR
P1M P4M P5M
; Set all ports to be input mode.
MOV B0MOV B0MOV B0MOV
A, #0FFH P1M, A P4M, A P5M, A
; Set all ports to be output mode.
B0BCLR B0BSET
P1M.1 P1M.1
; Set P1.1 to be input mode. ; Set P1.1 to be output mode.
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THE P0.3~P0.5 DISCRIPTION
The P0.3~P0.5 are input pins and shared with COM0~COM2 LCD driver pins. These input pins must work without LCD. To set the LCD code option to disable mode, the P0.3~P0.5's input function will be enabled. Input data be store in P0 data register.
Port0.3~P0.5 structure
PUR P0UR Int. bus
Pin LCD waveform
LCD Code Option
Figure 11-2. P0.3~P0.5 Block Diagram
Example: Enable P0.3~P0.5 input function. Step1: Disable the LCD controller of Code Option. Step2: Disable the LCD driver by LCD control bit.
B0BCLR
FLENB
; Disable LCD driver.
Step3: Now the P0.3~P0.5 general input function is enable. User can read P0.3~P0.5 input value using read instruction.
B0MOV
A,P0
; The bit3~bit5 are P0.3~P0.5 value.
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THE PORT2 DISCRIPTION
The port 2 is output only pins and shared with SEG16~SEG23 LCD driver pins. The port2 must works without LCD. To set the LCD code option to disable mode, the port 2 output function will be enabled. Output data from P2 is by P2 data register.
Port2 structure Latch Pin LCD waveform
LCD Code Option Int. bus
Figure 11-3. Port 2 Block Diagram
Example: Enable PORT 2 output function. Step1: Disable the LCD controller of Code Option. Step2: Disable the LCD driver by LCD control bit.
B0BCLR
FLENB
; Disable LCD driver.
Step3: Now the PORT 2 general output function is enable. User can output data by PORT 2.
B0MOV B0MOV
A, BUF P2, A
; Output BUF value to Port 2.
NOTE: The PORT 2 register (P2) is write-only register and doesn't support bit set/clear/test instruction.
B0BSET B0BCLR B0BTS1 B0BTS0
P2.0 P2.0 P2.0 P2.0
; ERROR!! Bit set instruction. ; ERROR!! Bit clear instruction. ; ERROR!! Bit 1 test instruction. ; ERROR!! Bit 0 test instruction.
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THE PORT3 DISCRIPTION
The port 3 is input only pins and shared with SEG8~SEG15 LCD driver pins. The port3 can work with LCD working. To set the bit1 of OPTION register (P3LCD) be "1", the port 3 input function will be enabled. The port3 input is with pull-up resistors.
Port3 structure
PUR
Int. bus
Pin LCD waveform
P3LCD
Figure 11-4. Port 3 Block Diagram
OPTION Register
OPTION initial value = xxxx xx00
088H OPTION
Bit 7 -
Bit 6 -
Bit 5 -
Bit 4 -
Bit 3 -
Bit 2 -
Bit 1 P3LCD R/W
Bit 0 RLCK R/W
P3LCD: P3 input function control bit. 0 = LCD driver pin, 1 = input port.
Example: Enable PORT 3 output function. Step1: Enable the P3 general input function by P3LCD control bit ("1").
B0BSET
FP3LCD
; Enable P3 general input function.
Step2: Now the PORT 3 general input function is enable. User can read data by PORT 3.
B0MOV
A, P3
; Read P3 value.
NOTE: The PORT 3 register (P3) is read-only register and doesn't support bit set/clear instruction.
B0BSET B0BCLR
P3.0 P3.0
; ERROR!! Bit set instruction. ; ERROR!! Bit clear instruction.
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THE PORT6 DISCRIPTION
The port 6 is I/O pins and shared with SEG0~SEG7 LCD driver pins. The port6 can work with LCD working. To set the bit1 of LCDM register (P6HSEG) be "1", the high-nibble of port 6 I/O function will be enabled. To set the bit0 of LCDM register (P6LSEG) be "1", the low-nibble of port 6 I/O function will be enabled. Setting the port6 direction is by P6M register. When Port6 is set to input mode, a pull-up register is connected automatic.
Port6 structure
PnM PnM
Pin
P6HSEG, P6LSEG PnM
Latch
Int. bus
PnM
LCD waveform
Figure 11-5. Port 6 Block Diagram
LCDM Register
LCDM register initial value = xx0x 0x00
0CBH LCDM
Bit 7 -
Bit 6 -
Bit 5 BLANK R/W
Bit 4 -
Bit 3 LENB R/W
Bit 2 -
Bit 1 P6HSEG R/W
Bit 0 P6LSEG R/W
P6LSEG : The lower 4 pins of Port6 control bit. 0 = Segment pins, 1 = general purpose I/O pins. P6HSEG : The higher 4 pins of port6 control bit. 0 = Segment pins, 1 = general purpose I/O pins.
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Example: Enable PORT 6 general input function.
; Set P6 as input port B0BSET B0BSET CLR MOV B0MOV
FP6HSEG FP6LSEG P6M A,#0FFH A,P6
; Set P6 high-nibble to be I/O mode. ; Set P6 low-nibble to be I/O mode. ; Set P6 to be input
; Read data from P6
. .
Example: Enable PORT 6 general output function.
; Set P6 as output port B0BSET B0BSET MOV B0MOV MOV B0MOV
FP6HSEG FP6LSEG A,#0FFH P6M,A A,#0FFH P6,A
; Set P6 high-nibble to be I/O mode. ; Set P6 low-nibble to be I/O mode.
; Set P6 to be output
; Output data to P6
. .
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I/O PORT DATA REGISTER
P0 initial value = xxx0 0000
0D0H P0
Bit 7 -
Bit 6 -
Bit 5 P05 R
Bit 4 P04 R
Bit 3 P03 R
Bit 2 P02 R
Bit 1 P01 R
Bit 0 P00 R
P1 initial value = xxxx 0000
0D1H P1
Bit 7 -
Bit 6 -
Bit 5 -
Bit 4 -
Bit 3 P13 R/W
Bit 2 P12 R/W
Bit 1 P11 R/W
Bit 0 P10 R/W
P2 initial value = 0000 0000
0D2H P2
Bit 7 P27 R/W
Bit 6 P26 R/W
Bit 5 P25 R/W
Bit 4 P24 R/W
Bit 3 P23 R/W
Bit 2 P22 R/W
Bit 1 P21 R/W
Bit 0 P20 R/W
P3 initial value = 0000 0000
0D3H P3
Bit 7 P37 R
Bit 6 P36 R
Bit 5 P35 R
Bit 4 P34 R
Bit 3 P33 R
Bit 2 P32 R
Bit 1 P31 R
Bit 0 P30 R
P4 initial value = 0000 0000
0D4H P4
Bit 7 P47 R/W
Bit 6 P46 R/W
Bit 5 P45 R/W
Bit 4 P44 R/W
Bit 3 P43 R/W
Bit 2 P42 R/W
Bit 1 P41 R/W
Bit 0 P40 R/W
P5 initial value = xxx0 0000
0D5H P5
Bit 7 -
Bit 6 -
Bit 5 -
Bit 4 P54 R/W
Bit 3 P53 R/W
Bit 2 P52 R/W
Bit 1 P51 R/W
Bit 0 P50 R/W
P6 initial value = 0000 0000
0D6H P6
Bit 7 P67 R/W
Bit 6 P66 R/W
Bit 5 P65 R/W
Bit 4 P64 R/W
Bit 3 P63 R/W
Bit 2 P62 R/W
Bit 1 P61 R/W
Bit 0 P60 R/W
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Example: Read data from input port.
B0MOV B0MOV B0MOV B0MOV
A, P0 A, P1 A, P4 A, P5
; Read data from Port 0 ; Read data from Port 1 ; Read data from Port 4 ; Read data from Port 5
Example: Write data to output port.
MOV B0MOV B0MOV B0MOV B0MOV
A, #55H P1, A P2, A P4, A P5, A
; Write data 55H to Port 1, Port 2, Port4 and Port 5
Example: Write one bit data to output port.
B0BSET B0BSET B0BCLR B0BCLR
P2.3 P4.0 P2.3 P5.1
; Set P2.3 and P4.0 to be "1".
; Set P2.3 and P5.1 to be "0".
Example: Port bit test.
B0BTS1 . B0BTS0
P0.0 P1.1
; Bit test 1 for P0.0 ; Bit test 0 for P1.1
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12 LCD DRIVER
There are 3 common pins and 24 segment pin in the SN8P1808. The LCD scan timing is 1/3 duty and 1/2 bias structure to yield 72 dots LCD driver. Of these pins, eight segment pins are shared with Port 6 and P6/SEG functions can be selected by programming LCDM register.
LCDM REGISTER
LCDM register initial value = xx0x 0x00
0CBH LCDM
Bit 7 -
Bit 6 -
Bit 5 BLANK R/W
Bit 4 -
Bit 3 LENB R/W
Bit 2 -
Bit 1 P6HSEG R/W
Bit 0 P6LSEG R/W
P6LSEG : The lower 4 pins of Port6 control bit. 0 = Segment pins, 1 = general purpose I/O pins. P6HSEG : The higher 4 pins of port6 control bit. 0 = Segment pins, 1 = general purpose I/O pins. LENB : LCD driver enables control bit. 0 = disable, 1 = enable. BLANK : LCD blanking control bit. 0 = normal display, 1 = all of the LCD dots off.
In following diagram, in order to get suitable contrast level of LCD panel, users can add external resistor to bias pin (V1, V2) to adjust bias voltage and LCD drive current. Too much or less current makes the LCD to bring remnant images. In normal condition, the external bias resistor value is 100K ohm. Users can connect a resistor between VLCD and VDD to adjust the voltage level at VLCD pin or just connect VLCD to VDD directly.
VDD
VLCD
R R
V2
R R
V1
BLANK LENB (LCDM.3) VSS
Figure 12-1. Adjust Circuit of LCD contrast
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LCD TIMING
F-frame = External Low clock / 384
Ex. External low clock is 32768Hz. The F-frame is 32768Hz/384 = 85.3Hz.
VDD
COM1
V2 V1=VSS
F-frame
VDD
COM2
V2 V1=VSS
VDD
COM3
V2 V1=VSS
VDD
SEG1
V2 V1=VSS
VDD
SEG1-COM1
V2 V1=VSS -V2 -VDD
Note: The clock source of LCD driver is external low clock.
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LCD RAM LOCATION
RAM bank 15's address vs. Common/Segment pin location COM0 COM1 COM2 SEG 0 00H.0 00H.1 00H.2 SEG 1 01H.0 01H.1 01H.2 SEG 2 02H.0 02H.1 02H.2 SEG 3 03H.0 03H.1 03H.2 SEG 14 0EH.0 0EH.1 0EH.2 SEG 15 0FH.0 0FH.1 0FH.2 SEG 16 10H.0 10H.1 10H.2 SEG 17 11H.0 11H.1 11H.2 SEG 21 15H.0 15H.1 15H.2 SEG 22 16H.0 16H.1 16H.2 SEG 23 17H.0 17H.1 17H.2 -
Example: Enable LCD function. Step1: Enable the LCD controller of Code Option to enable COM0~COM2, SEG16~SEG23. Step2: Enable the segment pin shared with PORT3 and PORT 6.
B0BCLR B0BCLR B0BCLR
FP3LCD FP6HSEG FP6LSEG
; Enable SEG8~SEG15 shared with PORT 3. ; Enable SEG4~SEG7 shared with P6.4~P6.7. ; Enable SEG0~SEG3 shared with P6.0~P6.3.
Step3: Now all LCD pins are enabled. Set the LCD control bit (LENB) and program LCD RAM to display LCD panel.
B0BSET . .
FLENB
; LCD driver.
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13 CONVERTER ANALOG TO DIGITAL 8-CHANNEL
OVERVIEW
This analog to digital converter of SN8P1800 has 8-input sources with up to 4096-step resolution to transfer analog signal into 12-bits digital data. The sequence of ADC operation is to select input source (AIN0 ~ AIN7) at first, then set GCHS and ADS bit to "1" to start conversion. When the conversion is complete, the ADC circuit will set EOC bit to "1" and final value output in ADB register. This ADC circuit can select between 8-bit and 12-bit resolution operation by programming ADLEN bit in ADR register.
AIN0/P4.0 AIN1/P4.1 AIN2/P4.2 DATA BUS AIN3/P4.3 AIN4/P4.4 AIN5/P4.5 AIN6/P4.6 AIN7/P4.7
Figure 13-1. AD Converter Function Diagram
A/D CONVERTER (ADC)
8/12
Note: For 8-bit resolution the conversion time is 12 steps. For 12-bit resolution the conversion time is 16 steps. Note: The analog input level must be between the AVREFH and AVSS. Note: The AVREFH level must be between the AVDD and AVSS.
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ADM REGISTER
ADM initial value = 0000 x000
0B1H ADM
Bit 7 ADENB R/W
Bit 6 ADS R/W
Bit 5 EOC R/W
Bit 4 GCHS R/W
Bit 3 -
Bit 2 CHS2 R/W
Bit 1 CHS1 R/W
Bit 0 CHS0 R/W
CHS2, 1, 0: ADC input channels select bit. 000 = AIN0, 001 = AIN1, 010 = AIN2, 011 = AIN3, .. , 111 = AIN7. GCHS: Global channel select bit. 0 = To disable AIN channel, 1 = To enable AIN channel. EOC: ADC status bit. 0 = Progressing, 1 = End of converting and reset ADENB bit. ADS: ADC start bit. 0 = stop, 1 = starting. ADENB: ADC control bit. 0 = disable, 1 = enable.
ADR REGISTERS
ADR initial value = x000 0000
0B3H ADR
Bit 7 0 -
Bit 6 ADCKS1 R/W
Bit 5 ADLEN R/W
Bit 4 ADCKS0 -
Bit 3 ADB3 R
Bit 2 ADB2 R
Bit 1 ADB1 R
Bit 0 ADB0 R
ADBn: ADC data buffer. ADB11~ADB4 bits for 8-bit ADC. ADB11~ADB0 bits for 12-bit ADC. ADLEN: ADC's resolution select bits. 0 = 8-bit, 1 = 12-bit. ADCKS0, ADCKS1: ADCKS1 ADCKS0 ADC Clock Source Note 0 0 Fcpu/4 Both validate in Normal mode and Slow mode 0 1 Fcpu/2 Both validate in Normal mode and Slow mode 1 0 Fhosc Only validate in Normal mode 1 1 Fhosc/2 Only validate in Normal mode
ADB REGISTERS
ADB initial value = xxxx xxxx
0B2H ADB
Bit 7 ADB11 R
Bit 6 ADB10 R
Bit 5 ADB9 R
Bit 4 ADB8 R
Bit 3 ADB7 R
Bit 2 ADB6 R
Bit 1 ADB5 R
Bit 0 ADB4 R
ADB is ADC data buffer to store AD converter result. The ADB is only 8-bit register including bit 4~bit11 ADC data. To combine ADB register and the low-nibble of ADR will get full 12-bit ADC data buffer. The ADC buffer is a read-only register. In 8-bit ADC mode, the ADC data is stored in ADB register. In 12-bit ADC mode, the ADC data is stored in ADB and ADR registers.
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The AIN's input voltage v.s. ADB's output data
ADB1 ADB10 ADB9 1 0/4096*AVREFH 0 0 0 1/4096*AVREFH 0 0 0 . . . . . . . . . . . . 4094/4096*AVREFH 1 1 1 4095/4096*AVREFH 1 1 1 AIN n
ADB8 0 0 . . . 1 1
ADB7 0 0 . . . 1 1
ADB6 0 0 . . . 1 1
ADB5 0 0 . . . 1 1
ADB4 0 0 . . . 1 1
ADB3 0 0 . . . 1 1
ADB2 0 0 . . . 1 1
ADB1 0 0 . . . 1 1
ADB0 0 1 . . . 0 1
For different applications, users maybe need more than 8-bit resolution but less than 12-bit ADC converter. To process the ADB and ADR data can make the job well. First, the AD resolution must be set 12-bit mode and then to execute ADC converter routine. Then delete the LSB of ADC data and get the new resolution result. The table is as following.
ADC ADB11 Resolution 8-bit O 9-bit O 10-bit O 11-bit O 12-bit O O = Selected, x = Delete
ADB
ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 ADB3
ADR
ADB2 ADB1 ADB0
O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
O O O O O
x O O O O
x x O O O
x x x O O
x x x x O
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ADC CONVERTING TIME
12-bit ADC conversion time = 1/(ADC clock /4)*16 sec 8-bit ADC conversion time = 1/(ADC clock /4)*12 sec
High clock (fosc) is @3.58MHz
ADLEN 0 (8-bit)
1 (12-bit)
ADCKS1 0 0 1 1 0 0 1 1
ADCKS0 0 1 0 1 0 1 0 1
ADC Clock fcpu/4 fcpu/2 fhosc fhosc/2 fcpu/4 fcpu/2 fhosc fhosc/2
ADC conversion time 1/((3.58MHz/4)/4/4)*12 = 214.5 us 1/((3.58MHz/4)/2/4)*12 = 107.3 us 1/(3.58MHz/4)*12 = 13.4 us 1/(3.58MHz/2/4)*12 = 26.8 us 1/((3.58MHz/4)/4/4)*16 = 286 us 1/((3.58MHz/4)/2/4)*16 = 143 us 1/(3.58MHz/4)*16 = 17.9 us 1/(3.58MHz/2/4)*16 = 35.8 us
Example : To set AIN0 ~ AIN1 for ADC input and executing 12-bit ADC
ADC0: MOV B0MOV MOV B0MOV B0BSET WADC0: B0BTS1 JMP B0MOV ADC1: MOV B0MOV B0BSET . QEXADC: B0BCLR FGCHS ; To release AINx input channel A,#91H ADM,A FADS . ; ; To enable ADC and set AIN1 input ; To start conversion . FEOC WADC0 A,ADB ; To skip, if end of converting =1 ; else, jump to WADC0 ; To get AIN0 input data A, #60H ADR, A A,#90H ADM,A FADS ; To set 12-bit ADC and ADC clock = Fosc. ; To enable ADC and set AIN0 input ; To start conversion
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ADC CIRCUIT
VDD AVREF Analog Signal Input 0.1uF AIN0/P40
MCU
AVREFH is connected to VDD.
VDD Reference Voltage Input Analog Signal Input 47uF 0.1uF AVREF AIN0/P40
MCU
AVREFH is connected to external AD reference voltage. Figure 13-2. The AINx and AVREFH Circuit of AD Converter
Note: The capacitor between AIN and GND is a bypass capacitor. It is helpful to stable the analog signal. Users can omit it.
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CODING ISSUE
TEMPLATE CODE
;******************************************************************************* ; FILENAME : TEMPLATE.ASM ; AUTHOR : SONiX ; PURPOSE : Template Code for SN8X180X ; REVISION : 09/01/2002 V1.0 First issue ;******************************************************************************* ;* (c) Copyright 2002, SONiX TECHNOLOGY CO., LTD. ;******************************************************************************* CHIP SN8P1808 ; Select the CHIP ;------------------------------------------------------------------------------; Include Files ;------------------------------------------------------------------------------.nolist ; do not list the macro file INCLUDESTD INCLUDESTD INCLUDESTD .list MACRO1.H MACRO2.H MACRO3.H ; Enable the listing function
;------------------------------------------------------------------------------; Constants Definition ;------------------------------------------------------------------------------; ONE EQU 1 ;------------------------------------------------------------------------------; Variables Definition ;------------------------------------------------------------------------------.DATA org DS DS DS DS org DS 0h 1 1 1 1 100h 20 ;Bank 0 data section start from RAM address 0x000 ;Temporary buffer for main loop ;Temporary buffer for ISR ;Accumulater buffer ;PFLAG buffer ;Bank 1 data section start from RAM address 0x100 ;Temporary buffer in bank 1
Wk00B0 Iwk00B0 AccBuf PflagBuf
BufB1
;------------------------------------------------------------------------------; Bit Flag Definition ;------------------------------------------------------------------------------Wk00B0_0 EQU Wk00B0.0 ;Bit 0 of Wk00B0 Iwk00B0_1 EQU Iwk00B0.1 ;Bit 1 of Iwk00
;-------------------------------------------------------------------------------
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; Code section ;------------------------------------------------------------------------------.CODE ORG jmp ORG jmp 0 Reset 8 Isr ;Code section start ;Reset vector ;Address 4 to 7 are reserved ;Interrupt vector
ORG 10h ;------------------------------------------------------------------------------; Program reset section ;------------------------------------------------------------------------------Reset: mov A,#07Fh ;Initial stack pointer and b0mov STKP,A ;disable global interrupt b0mov PFLAG,#00h ;pflag = x,x,x,x,x,c,dc,z b0mov RBANK,#00h ;Set initial RAM bank in bank 0 mov A,#40h ;Clear watchdog timer and initial system mode b0mov OSCM,A call call b0bset ClrRAM SysInit FGIE ;Clear RAM ;System initial ;Enable global interrupt
;------------------------------------------------------------------------------; Main routine ;------------------------------------------------------------------------------Main: b0bset FWDRST ;Clear watchdog timer call jmp MnApp Main
;------------------------------------------------------------------------------; Main application ;------------------------------------------------------------------------------MnApp: ; Put your main program here ret ;----------------------------------; Jump table routine ;----------------------------------ORG 0x0100 ;The jump table should start from the head ;of boundary. b0mov A,Wk00 and A,#3 ADD PCL,A jmp JmpSub0 jmp JmpSub1 jmp JmpSub2 ;-----------------------------------
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JmpSub0: ; Subroutine 1 jmp JmpExit JmpSub1: ; Subroutine 2 jmp JmpExit JmpSub2: ; Subroutine 3 jmp JmpExit JmpExit: ret
;Return Main
;------------------------------------------------------------------------------; Isr (Interrupt Service Routine) ; Arguments : ; Returns : ; Reg Change: ;------------------------------------------------------------------------------Isr: ;----------------------------------; Save ACC and system registers ;----------------------------------b0xch A,AccBuf ;B0xch instruction do not change C,Z flag push ; Save 80h ~ 87h system ;----------------------------------; Check which interrupt happen ;----------------------------------IntP00Chk: b0bts1 jmp b0bts0 jmp
FP00IEN IntTc0Chk FP00IRQ P00isr
;Modify this line for another interrupt
;If necessary, insert another interrupt checking here IntTc0Chk: b0bts1 jmp b0bts0 jmp
FTC0IEN IsrExit FTC0IRQ TC0isr
;Suppose TC0 is the last interrupt which you ;want to check
;----------------------------------; Exit interrupt service routine ;----------------------------------IsrExit: pop b0xch reti ; Restore 80h ~ 87h system registers ;B0xch instruction do not change C,Z flag ;Exit the interrupt routine
A,AccBuf
;-------------------------------------------------------------------------------
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; INT0 interrupt service routine ;------------------------------------------------------------------------------P00isr: b0bclr FP00IRQ ;Process P0.0 external interrupt here jmp IsrExit
;------------------------------------------------------------------------------; TC0 interrupt service routine ;------------------------------------------------------------------------------TC0isr: b0bclr FTC0IRQ ;Process TC0 timer interrupt here jmp IsrExit
;------------------------------------------------------------------------------; SysInit ; Initialize I/O, Timer, Interrupt, etc. ;------------------------------------------------------------------------------SysInit: ret ;------------------------------------------------------------------------------; ClrRAM ; Use index @YZ to clear RAM (00h~7Fh) ;------------------------------------------------------------------------------ClrRAM: ; RAM Bank 0 clr b0mov ClrRAM10: clr decms jmp clr ; RAM Bank 1 mov b0mov b0mov ClrRAM20: clr decms jmp clr ret
Y Z,#0x7f
;Select bank 0 ;Set @YZ address from 7fh
@YZ Z ClrRAM10 @YZ
;Clear @YZ content ;z = z - 1 , skip next if z=0 ;Clear address 0x00
A,#1 Y,A Z,#0x7f
;Select bank 1 ;Set @YZ address from 17fh
@YZ Z ClrRAM20 @YZ
;Clear @YZ content ;z = z - 1 , skip next if z=0 ;Clear address 0x100
;------------------------------------------------------------------------------ENDP
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CHIP DECLARATION IN ASSEMBLER
Assembler CHIP SN8P1808 OTP Device Part Number SN8P1808 MASK Device Part Number N/A
PROGRAM CHECK LIST
Item
Pull-up Resister
Description
Use @SET_PUR macro or PnUR register to enable or disable on-chip pull-up resisters. Refer I/O port chapter for detailed information.
Undefined Bits ADC SIO Master Mode SIO Slave Mode PWM0 PWM1 Interrupt Non-Used I/O Sleep Mode Stack Buffer
All bits those are marked as "0" (undefined bits) in system registers should be set "0" to avoid unpredicted system errors. Set ADC input pin I/O direction as input mode and disable pull-up resister of ADC input pin Set SCK (P5.0) and SO (P5.2) pin as output mode. Set SI (P5.1) pin as input mode. Set SO (P5.2) pin as output mode. Set SCK (P5.0) and SI (P5.1) pin as input mode. Set PWM0 (P5.4) pin as output mode. Set PWM1 (P5.3) pin as output mode. Do not enable interrupt before initializing RAM. Non-used I/O ports should be pull-up or pull-down in input mode, or be set as low in output mode to save current consumption. Enable on-chip pull-up resisters of port 0 and port 1 to avoid unpredicted wakeup. Be careful of function call and interrupt service routine operation. Don't let stack buffer overflow or underflow. 1. Write 0x7F into STKP register to initial stack pointer and disable global interrupt
System Initial
2. Clear all RAM. 3. Initialize all system register even unused registers. 1. Enable OSG and High_Clk / 2 code option together 2. Enable the watchdog option to protect system crash.
Noisy Immunity
3. Non-used I/O ports should be set as output low mode 4. Constantly refresh important system registers and variables in RAM to avoid system crash by a high electrical fast transient noise. 5. Enable the LVD option to improve the power on reset or brown-out reset performance
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15
Field
M O V E MOV MOV B0MOV B0MOV MOV B0MOV XCH B0XCH MOVC ADC ADC ADD ADD B0ADD ADD SBC SBC SUB SUB SUB DAA MUL AND AND AND OR OR OR XOR XOR XOR SWAP SWAPM RRC RRCM RLC RLCM CLR BCLR BSET B0BCLR B0BSET CMPRS CMPRS INCS INCMS DECS DECMS BTS0 BTS1 B0BTS0 B0BTS1 JMP CALL RET RETI PUSH POP NOP A R I T H M E T I C
INSTRUCTION SET TABLE
Description
AM MA A M (bnak 0) M (bank 0) A AI M I, (M = only for Working registers R, Y, Z , RBANK & PFLAG) A M A M (bank 0) R, A ROM [Y,Z] A A + M + C, if occur carry, then C=1, else C=0 M A + M + C, if occur carry, then C=1, else C=0 A A + M, if occur carry, then C=1, else C=0 M A + M, if occur carry, then C=1, else C=0 M (bank 0) M (bank 0) + A, if occur carry, then C=1, else C=0 A A + I, if occur carry, then C=1, else C=0 A A - M - /C, if occur borrow, then C=0, else C=1 M A - M - /C, if occur borrow, then C=0, else C=1 A A - M, if occur borrow, then C=0, else C=1 M A - M, if occur borrow, then C=0, else C=1 A A - I, if occur borrow, then C=0, else C=1 To adjust ACC's data format from HEX to DEC. R, A A * M, The LB of product stored in Acc and HB stored in R register. ZF affected by Acc. A A and M M A and M A A and I A A or M M A or M A A or I A A xor M M A xor M A A xor I A (b3~b0, b7~b4) M(b7~b4, b3~b0) M(b3~b0, b7~b4) M(b7~b4, b3~b0) A RRC M M RRC M A RLC M M RLC M M0 M.b 0 M.b 1 M(bank 0).b 0 M(bank 0).b 1 ZF,C A - I, If A = I, then skip next instruction ZF,C A - M, If A = M, then skip next instruction A M + 1, If A = 0, then skip next instruction M M + 1, If M = 0, then skip next instruction A M - 1, If A = 0, then skip next instruction M M - 1, If M = 0, then skip next instruction If M.b = 0, then skip next instruction If M.b = 1, then skip next instruction If M(bank 0).b = 0, then skip next instruction If M(bank 0).b = 1, then skip next instruction PC15/14 RomPages1/0, PC13~PC0 d Stack PC15~PC0, PC15/14 RomPages1/0, PC13~PC0 d PC Stack PC Stack, and to enable global interrupt To push working registers (080H~087H) into buffers To pop working registers (080H~087H) from buffers No operation
Mnemonic
A,M M,A A,M M,A A,I M,I A,M A,M A,M M,A A,M M,A M,A A,I A,M M,A A,M M,A A,I A,M A,M M,A A,I A,M M,A A,I A,M M,A A,I M M M M M M M M.b M.b M.b M.b A,I A,M M M M M M.b M.b M.b M.b d d
C
-
DC
-
Z
-
Cycle
1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1+S 1+S 1+S 1+S 1+S 1+S 1+S 1+S 1+S 1+S 2 2 2 2 1 1 1
L O G I C
P R O C E S S
B R A N C H
M I S C
Table 15-1. Instruction Set Table of SN8P1800 Note: Any instruction that read/write from 0SCM, will add an extra cycle.
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16 ELECTRICAL CHARACTERISTIC
ABSOLUTE MAXIMUM RATING
(All of the voltages referenced to Vss) Supply voltage (Vdd)............................................................................................................... - 0.3V ~ 6.0V Input in voltage (Vin)..................................................................................................Vss - 0.2V ~ Vdd + 0.2V Operating ambient temperature (Topr)......................................................................................-20C ~ + 70C Storage ambient temperature (Tstor).......................................................................................-30C ~ + 125C Power consumption (Pc).................................................................................................................500 mW
STANDARD ELECTRICAL CHARACTERISTIC
(All of voltages referenced to Vss, Vdd = 5.0V, fosc = 3.579545 MHz, ambient temperature is 25C unless otherwise note.) PARAMETER SYM. DESCRIPTION MIN. TYP. MAX. UNIT
Operating voltage RAM Data Retention voltage Internal POR Input Low Voltage Vdd Vdr Vpor ViL1 ViL2 ViL3 ViL4 ViH1 ViH2 ViH3 ViH4 Ilekg Rup Ilekg IoH IoL IoH IoL IoH IoL IoH IoL IoH IoL Tint0 Varfh Varfl Vani V3/3 V2/3 V1/3 Zlcd flcdm1 Vlcd Idd1 Supply Current (Disable ADC and LVD) Idd2 Idd3 Idd4 ADC current consumption LVD Detect Voltage Voltage detector current IADC Vdet Ivdet Normal mode, Vpp = Vdd Programming mode, Vpp = 12.5V Vdd rise rate to ensure internal power-on reset All input pins except those specified below Input with Schmitt trigger buffer - Port0 Reset pin ; Xin ( in RC mode ) Xin ( in X'tal mode ) All input pins except those specified below Input with Schmitt trigger buffer - Port0 Reset pin ; Xin ( in RC mode ) Xin ( in X'tal mode ) Vin = Vdd Vin = Vss , Vdd = 5V Pull-up resistor disable, Vin = Vdd Vop = Vdd - 0.5V Vop = Vss + 0.5V Vop = Vdd - 0.5V Vop = Vss + 0.5V Vop = Vdd - 0.5V Vop = Vss + 0.5V Vop = Vdd - 0.5V Vop = Vss + 0.5V Vop = Vdd - 0.5V Vop = Vss + 0.5V INT0 ~ INT2 interrupt request pulse width Vdd = 5.0V Vdd = 5.0V 2.4 4.5 Vss Vss Vss Vss 0.7Vdd 0.8Vdd 0.9Vdd 0.7Vdd 2/fcpu Varfl+1.2V Vss Varfl 5.0 5.0 1.5 0.05 100 12 15 12 15 12 15 12 15 12 15 1 2/3 1/3 1.2 64 7 1.5 50 100 30 10 3 40 10 0.6 0.4 2.4 100 5.5 5.5 0.3Vdd 0.2Vdd 0.2Vdd 0.3Vdd Vdd Vdd Vdd Vdd 2 2 Vdd Varfh-1.2V Varfh Vdd 15 3 100 200 60 20 6 80 20 1 0.8 180 V V V/ms V V V V V V V V uA K uA mA mA mA mA mA cycle V V V VLCD M Hz V mA mA uA uA uA uA uA uA uA mA mA V uA
Input High Voltage
Reset pin leakage current I/O port pull-up resistor I/O port input leakage current Port1 output source current sink current Port2 output source current sink current Port4 output source current sink current Port5 output source current sink current Port6 output source current sink current INTn trigger pulse width AVREFH input voltage AVREFL input voltage AIN0 ~ AIN7 input voltage COM, SEG pin Output voltage LCD bias dividing resistor LCD frame frequency LCD Voltage
Each section resistor, Vdd = 5.0V
Run Mode
Slow Mode (High clock stop LCD off) Vdd= 3V 32768Hz Vdd= 5V Sleep mode Vdd= 3V Green Mode Vdd= 5V 32768Hz (High clock stop LCD off) Vdd= 3V 32768Hz Vdd=5.0V Vdd=3.0V Low voltage detect level LVD enable operating current
Vdd= 5V Vdd= 3V Vdd= 3V Vdd= 5V
4Mhz 4Mhz 32768Hz 32768Hz
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17
LQFP64:
PACKAGE INFORMATION
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SYMBLE MIN. A A1 A2 b b1 c c1 D D1 E E1 [e] L L1 R1 R2 Y 1 2 3
DIMENSION (MM) NOM. MAX. MIN.
DIMENSION (MIL) NOM. MAX.
1.60 0.05 1.36 0.17 0.17 0.09 0.09 12.00 BSC 10.00 BSC 12.00 BSC 10.00 BSC 0.50 BSC 0.45 0.60 1.00 REF 0.08 0.08 0.20 0.075 0 0 11 11 12 12 13 13 3.5 7 0 0 11 11 12 12 3.5 3 3 0.75 18 1.40 0.22 0.22 0.15 1.45 0.27 0.23 0.20 0.16 2 35 7 7 4 4 472 BSC 394 BSC 472 BSC 394 BSC 20 BSC 24 39 REF 55 9 8
63 6 57 11 12 8 6
30
8 3 7
13 13
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers , employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.
Main Office:
Address: 9F, NO. 8, Hsien Cheng 5th St, Chupei City, Hsinchu, Taiwan R.O.C. Tel: 886-3-551 0520 Fax: 886-3-551 0523
Taipei Office:
Address: 15F-2, NO. 171, Song Ted Road, Taipei, Taiwan R.O.C. Tel: 886-2-2759 1980 Fax: 886-2-2759 8180
Hong Kong Office:
Address: Flat 3 9/F Energy Plaza 92 Granville Road, Tsimshatsui East Kowloon. Tel: 852-2723 8086 Fax: 852-2723 9179
Technical Support by Email:
Sn8fae@sonix.com.tw
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